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Altium Designer 17.0 brings with it a number of enhancements to PCB Design Rules. From simplification of the minimum clearance matrix, and the ability to check clearances between split planes, to hole-to-primitive clearance checking, and checking for bad connections as part of the Un-Routed Net rule, these improvements collectively enhance your ability to constrain your board designs exactly as needed.
The following enhancements have been implemented for the Clearance rule.
For many users, there is no great difference between Track and Arc primitives. And when it comes to Fill, Region, and Polygon objects, most users just see these as more 'copper'. With this in mind, the minimum clearance matrix for the Clearance rule has been enhanced to operate in two modes:
Simplifying the objects involved in the minimum clearance matrix by introducing a Simple mode.
Aspects of the feature to be aware of:
Streamlining DRC and reducing the clutter of error markers flagging violations that are not real, an option has been added to the Clearance rule's constraints that allows you to specify that clearances between pads in the same component footprint be ignored. This option - Ignore Pad to Pad clearances within a footprint - is disabled by default.
Prevent violations associated to pad clearances within the same component footprint, with the option to ignore such clearances.
Adding another element to its clearance checking capabilities, Altium Designer 17.0 brings the ability to check clearances between the edges of drill holes and neighboring copper objects on signal layers. An additional row is now available at the bottom of the Clearance rule's minimum clearance matrix with which to define the desired clearances. This is particularly beneficial in preventing the routing of track too near to a drilled hole, which could otherwise suffer from any potential wandering of the drill during board fabrication.
Set clearance values to catch any copper objects that are too close to the edges of drill holes in the design.
The Clearance rule in Altium Designer 17.0 also now supports checking of clearances between split plane regions on internal plane layers. How clearance is defined depends on the mode in which you are using the minimum clearance matrix:
A violation will appear in the form:
Clearance Constraint: (<CurrentClearance> < <DefinedClearance>) Between Polygon Region (<NumberOfHolesinRegion1> hole(s)) <InternalPlaneLayerName> And Polygon Region (<NumberOfHolesinRegion2> hole(s)) <InternalPlaneLayerName>,
for example:
Clearance Constraint: (20.173mil < 34mil) Between Polygon Region (0 hole(s)) Internal Plane 1 And Polygon Region (1 hole(s)) Internal Plane 1
Clearance checking between split plane regions on an internal layer. In this case, the clearance value of 34mil has been entered in the Region-Region cell, as clearances
are being defined using the Advanced mode of the matrix.
The PCB Editor's Design Rule Checking system typically sees a net as being routed if all nodes in that net (component pads) are connected through the use of net-aware design objects (tracks, arcs, pads, vias, polygons). These objects are considered connected if they touch each other. However, while simply touching makes a perceived connection to the software, when it comes time to fabricate the board, the fragility of some of these 'connections' can cause critical issues, especially where the objects - for example two contiguous track segments or a track entering a pad/via - are only slightly touching. Such connections are often referred to as 'Bad Connections,' 'Poor Connections,' or 'Incomplete Connections.'
In Altium Designer 17.0, enhanced checking for the existence of such fragile connectivity is available, courtesy of the Check Incomplete Connections option - a new constraint of the Un-Routed Net rule.
With this option enabled, the following additional checks on connectivity between applicable design objects are made:
A poor connection will be flagged in the workspace using the detailed violation marker, , with a corresponding message appearing in the Messages panel. As before, and where applicable, a connection line will be drawn between unconnected objects in the net, with data regarding the Unrouted net length reflected in the PCB panel (in Nets mode).
Catch poor connections in your designs as part of the enhanced Un-Routed Net rule.
The Power Plane Connect Style rule has been given two modes of operation in Altium Designer 17.0:
Roll the mouse over the image to compare the two modes available.
Aspects of the feature to be aware of:
The Polygon Connect Style rule has also been given two modes of operation in Altium Designer 17.0:
Roll the mouse over the image to compare the two modes available.
Aspects of the feature to be aware of:
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