Testpoint Rule Types

Updated: October 13, 2026

At a Glance

This article gives you a focused overview of the Testpoint design rule types available in Altium Designer, with an emphasis on the Fabrication Testpoint Style and Assembly Testpoint Style rules and how they define the physical pad and via parameters used for testpoint assignment. It also highlights an important requirement for successful use in the Testpoint Manager, namely that at least one corresponding Style rule must have a scope of All, while noting that the constraints for these two rules are identical. If you want a clearer understanding of how these testpoint rules are structured and what role they play in PCB layout, this article is a useful place to start, keep reading to build confidence in setting them up correctly.

- Learn what the Testpoint category covers in Altium Designer and which rule types are discussed.
- Understand the purpose of the Fabrication Testpoint Style and Assembly Testpoint Style rules in defining valid testpoint pads and vias.
- See the key requirement for Testpoint Manager assignment, including the need for at least one Style rule scoped to All.

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The design rules of the Testpoint category are described below.

The Testpoint category of design rules.

Fabrication and Assembly Testpoint Style

The Fabrication Testpoint Style and Assembly Testpoint Style design rules specify the allowable physical parameters of pads and vias that are to be considered for use as testpoints for bare-board fabrication testing, or in-circuit assembly testing respectively. The constraints between these two rules are identical.

For the Testpoint Manager to successfully assign testpoints, there must always be at least one corresponding Style rule with a scope of All.

Constraints

Constraint Manager – constraints for the Fabrication and Assembly Testpoint Style rule.

PCB Rules and Constraints Editor – constraints for the Fabrication and Assembly Testpoint Style rule.

Fabrication and Assembly Testpoint Style Constraint

Default Rule	Required i
Sizes	The following options allow you to specify pad/via diameter and hole size criteria when testing for valid testpoints: Min Size - specifies the minimum permissible diameter for a pad/via to be considered as a testpoint. Max Size - specifies the maximum permissible diameter for a pad/via to be considered as a testpoint. Preferred Size - specifies the diameter to be used for testpoint pads/vias placed by the Autorouter. Min Hole Size - specifies the minimum permissible hole size for a pad/via to be considered as a testpoint. To use a surface mount pad as a testpoint, the minimum hole size must be set to zero. Max Hole Size - specifies the maximum permissible hole size for a pad/via to be considered as a testpoint. Preferred Hole Size - specifies the hole size to be used for testpoint pads/vias placed by the Autorouter.
Clearances	The following options allow you to define clearance constraints specific to board testing: Min Inter-Testpoint Spacing - specifies the minimum permissible center-to-center distance to be observed between two adjacent testpoints, when considering a pad/via for use as a testpoint. This is typically determined by the probe head spacing for the flying probe, or bed-of-nails test fixtures, being used in the testing. Component Body Clearance - specifies the minimum permissible distance to be observed between a testpoint and the body of a component, when considering a pad/via for use as a testpoint. If a component has a component body, then the clearance is applied to the component body. If a component body is absent, then the clearance is applied to the component's non-pad/via primitive objects on the Mechanical + TopOverlay/BottomOverlay layers. Board Edge Clearance - specifies the minimum permissible distance to be observed between a testpoint and the edge of the board, when considering a pad/via for use as a testpoint. Distance to Pad Hole Centers - specifies the minimum permissible distance from the center of a testpoint, to the center of an adjacent pad (the center of the pad's hole). Distance to Via Hole Centers - specifies the minimum permissible distance from the center of a testpoint, to the center of an adjacent via (the center of the via's hole). The software checks the distance in accordance with the layer settings of the objects under test. For example, if a thru-hole pad is only configured to be a testpoint on the bottom layer, then the minimum clearance is not checked against other pads/vias on the top layer.
Grid	Use of a grid is most appropriate when targeting a non-custom bed-of-nails fixture. To include use of a grid, enable the Use Grid option. To disable use of a grid, enable the No Grid option. If you do want to use a grid, the following options allow you to define it in a more comprehensive manner: Origin - the X and Y coordinates, specified relative to the current board origin. This allows you to align the grid with the origin of a bed-of-nails fixture. Grid Size - specifies the size of the grid to be used when attempting to find valid testpoint sites (pads and/or vias). If the entry is changed to zero, the No Grid option will automatically be selected upon applying the change. Tolerance - specifies the maximum permissible tolerance to use when considering how far from a specified grid a pad or via can be located and still be considered a valid testpoint location. When specifying use of a grid, if a pad/via assigned as a testpoint is not on the grid specified by the Grid Size option, it will cause a violation when performing a Design Rule Check (DRC). For example, if you set the Grid Size to `25mil`, then the testpoints must be on a 25mil grid. If the testpoints do not lie on any particular grid, you can either enter a value for Grid Size that will accommodate all testpoints (the minimum setting is `0.001 mil`), or you can simply specify the No Grid option.
Allowed Side	Use these options to specify on which side of the board prospective testpoint pad/via locations can reside - either Top, Bottom, or both.
Allow Testpoint Under Component	Use this option to enable the use of pads/vias located underneath components (on the same side of the board as the components) for testpoint purposes. This option would typically be enabled in a Fabrication Testpoint Style rule, but not for an Assembly Testpoint Style rule - as the pad/via will typically not be accessible once the board is populated with components.
Rule Scope Helper	Use this region of the constraints to determine which objects the rule is to apply to. Simply enable the checkbox for the objects to be included - SMD Pads, Vias, Thru-hole Pads - and click on the Set Scope button. The logical query for the rule scope will be created and entered into the Full Query region for the rule. Note that the helper is only available in the PCB Rules and Constraints Editor.
Rule Application	This rule is obeyed by the Testpoint Manager, the Autorouter, the Online and Batch DRC, and during output generation. The Online DRC and Batch DRC test all attributes of the rule except the Preferred Size and Preferred Hole Size - these settings are used by the Autorouter to define the size of testpoint pads/vias that the Autorouter places.

Fabrication and Assembly Testpoint Usage

The Fabrication Testpoint Usage and Assembly Testpoint Usage design rules specify which nets require testpoints for bare-board fabrication testing, or in-circuit assembly testing, respectively. The constraints between these two rules are identical.

Constraints

Constraint Manager – constraints for the Fabrication and Assembly Testpoint Usage rule.

PCB Rules and Constraints Editor – constraints for the Fabrication and Assembly Testpoint Usage rule.

Fabrication and Assembly Testpoint Usage Constraint

Default Rule	Required i
Required	Each target net must have a testpoint assigned. You can further sub-specify whether: only a single testpoint is required for each net, or a testpoint is to be inserted at each leaf node in a target net (pad/via locations that terminate a route). In addition, you can specify that a target net can have more testpoints – these must be manually assigned.
Prohibited	Each target net must not have a testpoint assigned.
Don't Care	Each target net can have a testpoint assigned. It does not matter if a testpoint cannot be assigned to a net.
Assigning testpoints	Use the Testpoint Manager dialog to identify the status of testpoint coverage for each net in a design, both in terms of bare-board fabrication and in-circuit assembly testing. A DRC report, obtained from running a Batch DRC, can be used to identify each net that fails this rule.
Testpoint reports	Fabrication and Assembly Testpoint reports can be configured and generated along with other fabrication and assembly outputs, as part of an Output Job Configuration file (`*.OutJob`). Use these reports to interrogate the locations of all valid fabrication and assembly testpoints, assigned in the design, respectively.
Importing older designs	When opening/importing PCB designs created in a release of the software prior to the Summer 09 release, Testpoint Usage rules will become Fabrication Testpoint Usage rules.
Rule Application	This rule is obeyed by the Testpoint Manager, Autorouter, the Online and Batch DRC, and during output generation.

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Feature Availability

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Legacy Documentation

Altium Designer documentation is no longer versioned. If you need to access documentation for older versions of Altium Designer, visit the Legacy Documentation section of the Other Installers page.

Testpoint Rule Types

At a Glance

Fabrication and Assembly Testpoint Style

Constraints

Fabrication and Assembly Testpoint Usage

Constraints

Contents

Contents