Routing Rule Types

Specifies the preferred width to be used for tracks when routing the board.

Specifies the maximum permissible width to be used for tracks when routing the board.

For each route in the net targeted by the rule, check that the width of each individual track and arc falls within the minimum and maximum range ().

This option becomes available when at least one impedance profile is defined in the Layer Stack Manager. When enabled, use the drop-down to select the impedance profile desired.

When the rule is configured in this mode, the Preferred Width required on each routing layer is calculated as part of the specified impedance profile (Min Width and Max Width values will also be set to this value when the option is enabled). Once the rule is defined, as you route a net that falls under the scope of the rule, the track width will automatically be set to the width required to meet the specified impedance for that layer.

When this option is enabled, the Preferred Width cannot be edited in the rule, but the Min Width and Max Width values can.

Learn more about Configuring the Layer Stack for Controlled Impedance Routing.

This option appears when multiple layer stacks are defined in the Layer Stack Manager. If the board includes multiple layer stacks, then the Width Constraints must be configured for each stack, using either the all-layer fields above the image or the layer-specific fields in the Layer Attributes Table ( ).

Learn more about Defining and Configuring Substacks.

The grid region at the bottom of the dialog displays all signal layers defined in the layer stack unless the Use Impedance Profile option is enabled. If this option is enabled, then only the layers available as part of the selected impedance profile will be displayed.

The grid displays the minimum, maximum and preferred routing widths and other layer-specific information. The routing width fields can be set globally by defining the values in the constraint fields above the image or individually by typing values directly into the table.

When the Use Impedance Profile option is enabled, the required width entries will be automatically calculated and entered for each layer in the table. In this mode, the Preferred Width values cannot be edited, but the Min Width and Max Width values can.

• The Min Width and Max Width settings define the range of permissible values that can be used during interactive routing. Press the 3 shortcut to cycle through the Min, Preferred, Max, User Choice settings during routing, or press Tab to edit the trace width in the Properties panel. If a value is entered outside of the Min-Max range, it will automatically be clipped.

• The Preferred Width setting is obeyed by the Autorouter.

• The Min Width and Max Width settings define the lower and upper values used by the Online DRC and Batch DRC.

Defines the topology to be used for the net(s) targeted by the scope (full query) of the rule. The following topologies can be applied:

• Shortest - connect all nodes in the net to give the shortest overall connection length.

• Horizontal - connect all the nodes together, preferring horizontal shortness to vertical shortness by a factor of 5:1. Use this method to force routing in the horizontal direction.

• Vertical - connect all the nodes together, preferring vertical shortness to horizontal shortness by a factor of 5:1. Use this method to force routing in the vertical direction.

• Daisy-Simple - chain all the nodes together, one after the other. The order they are chained is calculated to give the shortest overall length. If a source and terminator pad are specified, then all other pads are chained between them to give the shortest possible length. Edit a pad to set it to be a source or terminator. If multiple sources (or terminators) are specified, they are chained together at each end.

• Daisy-MidDriven - place the source node(s) in the center of the daisy chain, then divide the loads equally and chain them off either side of the source(s). Two terminators are required, one for each end. Multiple source nodes are chained together in the center. If there are not exactly two terminators the Daisy-Simple topology is used.

• Daisy-Balanced - divide all the loads into equal chains, the total number of chains equal to the number of terminators. These chains then connect to the source in a star pattern. Multiple source nodes are chained together.

• Starburst - connect each node directly to the source node. If terminators are present, they are connected after each load node. Multiple source nodes are chained together, as in the Daisy-Balanced topology.

When using the Autorouter, the routing direction for each enabled signal layer in the design is defined as part of the Situs Autorouter setup. Directions are specified in the Layer Directions dialog, accessed by clicking the Edit Layer Directions button in the Situs Routing Strategies dialog.

Specifies which routing corner style to use. The following three styles are available:

• 90 Degrees

• 45 Degrees

• Rounded

These two fields allow you to define a minimum and maximum value for the setback when using the 45 Degrees and Rounded corner styles. The setback is the distance from the 'true' corner location (that which would exist if using the 90 Degrees style) to the point at which the Autorouter should begin its chamfering or rounding, effectively controlling miter size or corner radius.

Use the drop-down to choose from the following two modes:

• Min/Max preferred - choose this mode to set the permissible values (Minimum/Maximum/Preferred) for the via's diameter and hole size as part of the rule itself.

• Template preferred - choose this mode to be able to use via styles defined through via templates available to the board.

Mode = Min/Max preferred

(constraint settings)

Via Diameter - specifies the Minimum, Preferred and Maximum values of the diameter of vias placed during routing.

Via Hole Size - specifies the Minimum, Preferred and Maximum values of the hole sizes of vias placed during routing.

Mode = Min/Max preferred

(changing the via size during routing)

The Routing Via Style design rule defines the X-Y properties of the via. When a via is being placed during interactive routing, you can cycle through the Minimum / Preferred / Maximum / User Choice via definitions by pressing the 4 key. The currently selected state is displayed in the Heads-Up Display and on the Status bar. You can also press the Tab key while routing to access the Properties panel, where you can edit the via properties within the Min/Max rule range. If a value is entered outside of its range, it will automatically be clipped.

Mode = Template preferred

(constraint settings)

Templates List - lists the available via templates that can be used with the rule. These are via templates (local or defined in Pad Via Template Libraries) that are made available to the board design as part of the Local Pad & Via Library (accessed through the PCB Pad Via Templates panel). For each available template, the following information is presented:

• Template Name - the read-only name of the template. For a local template, auto-generated naming is used in compliance with IPC standards. For a template sourced from a PvLib, this naming can be customized as part of template configuration within that library.

• Description - the read-only description written for the template.

• Library - the library from which the template is sourced. This can be <Local> (where the via is defined and saved with the PCB document) or the name of the external Pad Via Template Library (<LibraryName>.PvLib) which has been made available to the PCB document.

• Enabled - enable this option to have the template made available for via placement during Interactive Routing.

Mode = Template preferred

(changing the via size during routing)

When a routing via is about to be placed during interactive routing, you can cycle through the enabled via templates by pressing the 4 key. The selected template is displayed in the Heads-Up Display and on the Status bar. You can also press the Tab key while routing to access the Properties panel, from where you can change the via template currently applied.

In order to control the size of blind and buried vias, individual rules can be set up targeting the different layer pairs. For example, to control the via size for blind vias between the top layer and mid-layer 1, the following scope (Full Query) can be used:

(StartLayer = 'Top Layer') and (StopLayer = 'Mid-Layer1')

To control the via size for buried vias between mid-layer 2 and mid-layer 3, the following scope would be used:

(StartLayer = 'Mid-Layer2') and (StopLayer = 'Mid-Layer3')

Alternatively, instead of creating individual rules, you can expand the one rule query using ORs as follows:

((StartLayer = 'Top Layer') and (StopLayer = 'Mid-Layer1')) or((StartLayer = ' Mid-Layer2') and (StopLayer = 'Mid-Layer3'))

Online DRC, Batch DRC, during autorouting, and during interactive routing. When the mode of the rule is set to Min/Max preferred, the following considerations apply:

• The Preferred via attributes are used by the Autorouter.

• The Minimum and Maximum via attributes are obeyed by the Online DRC and Batch DRC.

Specifies how the fanout vias are placed in relation to the SMT component. The following options are available:

• Auto - chooses the style most appropriate for the component technology in order to give optimal routing space results.

• Inline Rows - fanout vias are placed within two aligned rows.

• Staggered Rows - fanout vias are placed within two staggered rows.

• BGA - fanout occurs in accordance with the specified BGA Options.

• Under Pads - fanout vias are placed directly under SMT component pads.

Specifies the direction to use for the fanout. The following options are available:

• Disable - do not allow fanout with respect to the SMT components targeted by the rule.

• In Only - fanout in an inward direction only. All fanout vias and connecting track will be placed within the component's bounding rectangle.

• Out Only - fanout in an outward direction only. All fanout vias and connecting track will be placed outside of the component's bounding rectangle.

• In Then Out - fanout all component pads in an inward direction to begin with. All pads that cannot be fanned out in this direction should be fanned out in an outward direction (if possible).

• Out Then In - fanout all component pads in an outward direction to begin with. All pads that cannot be fanned out in this direction should be fanned out in an inward direction (if possible).

• Alternating In and Out - fanout all component pads (where possible) in an alternating fashion, first inward then outward.

Specifies the direction to use for the fanout. When a BGA component is fanned out, its pads are sectioned into quadrants, with fanout applied to the pads in each quadrant simultaneously. The following options are available:

• Away From Center - fanout for pads in each quadrant is applied following a 45° angle away from the component's center.

• North-East - all pads in each quadrant are fanned out in a North-Easterly direction (45° anti-clockwise from the horizontal).

• South-East - all pads in each quadrant are fanned out in a South-Easterly direction (45° clockwise from the horizontal).

• South-West - all pads in each quadrant are fanned out in a South-Westerly direction (135° clockwise from the horizontal).

• North-West - all pads in each quadrant are fanned out in a North-Westerly direction (135° anti-clockwise from the horizontal).

• Towards Center - fanout for pads in each quadrant is applied following a 45° angle toward the component's center. In most cases, uniformity of direction will not be possible due to the required fanout space already taken by another pad's fanout via. In these cases, fanout will occur in the next available direction (North-East, South-East, South-West, North-West).

Specifies how the fanout vias are placed in relation to the pads of the BGA component. The following options are available:

• Close To Pad (Follow Rules) - fanout vias will be placed as close to their corresponding SMT component pads as possible without violating defined clearance rules.

• Centered Between Pads - fanout vias will be centered between the SMT component pads.

The following default Fanout Control design rules are automatically created, covering the typical component package types available (listed in descending order of priority). These rules can be edited or others can be defined in accordance with your individual design requirements.

• Fanout_BGA – with a query of IsBGA.

• Fanout_LCC - with a query of IsLCC.

• Fanout_SOIC - with a query of IsSOIC.

• Fanout_Small - with a query of (CompPinCount < 5).

• Fanout_Default - with a query of All.

This option becomes available when at least one impedance profile is defined in the Layer Stack Manager. When enabled, use the drop-down to select the required impedance profile. When the rule is configured in this mode, the Preferred Width and Preferred Gap required on each routing layer are calculated as part of the specified impedance profile. Once the rule is defined, as you route a differential pair that falls under the scope of the rule, the track widths and pair gap will automatically be set to the values required for that layer to meet the specified impedance.

Learn more about Configuring the Layer Stack for Controlled Impedance Routing.

This option appears in the dialog when there are multiple layer stacks defined in the Layer Stack Manager. If the board includes multiple layer stacks, then the Differential Pairs Routing Constraints must be configured for each of the layer stacks, using either the all-layer fields above the image, or the layer-specific fields in the Layer Attributes Table, or by selecting an impedance profile.

Learn more about Defining and Configuring Substacks.

The grid region at the bottom of the dialog displays all signal layers defined in the layer stack, unless an Impedance Profile is selected. If it is, then only the layers available as part of the selected impedance profile will be displayed. The minimum, maximum and preferred width and gap constraints and other layer-specific information are displayed. The routing Width and Gap fields can be set globally by defining the values in the constraint fields above the image or individually by typing values directly into the table. When an Impedance Profile is selected, the required Preferred width entries are automatically calculated and entered for each layer in the table. In this mode, the Preferred Width and Preferred Gap values cannot be edited, but the Min and Max values can.

When defining values for the minimum, maximum and preferred width and/or gap, the Layer Attributes Table will highlight invalid entries using red text. This could happen, for example, when you specify a minimum constraint value that is greater than the maximum constraint value or when setting a preferred constraint value that is lower than the minimum or above the maximum constraint values. The incorrect rule definition is further highlighted by the rule name becoming red in both the folder-tree pane and the respective summary lists in the PCB Rules and Constraints Editor dialog.

While the width of each net in a differential pair is monitored by the applicable Differential Pairs Routing rule (and not by a Width rule), clearance checking between the nets in that pair is still governed by the applicable Clearance design rule. If the differential pair routing gap is less than the minimum clearance allowed between different nets on the board, the nets in the differential pairs will fail the clearance constraint. To avoid this, a separate clearance constraint must be created, setting the net-to-net clearance in differential pairs to the same value as the Diff Pair Gap. 

To do this in the Constraint Manager, set the Clearance value for the pairs to the same value as the Diff Pair Gap. This is demonstrated in the first slide of the Differential Pair Routing slideshow above, where the clearance for the differential pairs has been set to 0.12446mm.

To do this in the PCB Rules and Constraints Editor, add an additional Clearance constraint set to the same clearance value as the Diff Pair Gap, with the Same Differential Pair option selected. This is demonstrated in the fourth slide of the Differential Pair Routing slideshow above, where the clearance for the differential pairs has been set to 0.127mm.

While the optimal Width-Gap settings may be achievable for most of the board, there will often be areas, such as under a BGA component, where smaller and tighter Width-Gap settings must be used. Defining the Min Gap to be less than the Preferred Gap allows the router to bring the pair members closer to each other, where obstacles require this. While this works, it comes at a cost; routing operations become much more complicated and are, therefore, slower.

This requirement can also be achieved by defining multiple differential pair routing rules - a lower-priority rule that targets the differential pair across the board and a higher-priority rule that targets the differential pair in the specific area where a narrower Width-Gap setting is required. You then target the differential pair in that area by defining a Room Definition rule for that area and use that room as part of the scope of the differential pair routing rule that requires a tighter Width-Gap setting.

Online DRC, Batch DRC, interactive routing (and re-routing), autorouting, interactive length tuning (Min Gap is applied), and when interactively modifying the pair, such as sliding a track segment of one of the nets in the pair.