Creating Circuit Connectivity in Your Schematics in Altium NEXUS

This documentation page references Altium NEXUS/NEXUS Client (part of the deployed NEXUS solution), which has been discontinued. All your PCB design, data management and collaboration needs can now be delivered by Altium Designer and a connected Altium 365 Workspace. Check out the FAQs page for more information.

 

Parent page: Capturing Your Design Idea as a Schematic

It is the components and how they connect to each other that create your unique, electronic circuit. In the schematic, you create the logical representation of your design by connecting the component pins together; to design the printed circuit board, you place the physical components and create the same connectivity with the routing.

If you're learning how to structure your design and create connectivity, you might find the following pages helpful.

Learn about Verifying Your Design Project

Learn about Multi-sheet & Hierarchical Designs

Learn about Creating a Multi-channel Design

Learn about Bundling Multiple Nets into Buses & Signal Harnesses

Learn about Design Synchronization

Physical and Logical Connectivity

On the schematic, you can create that connectivity by drawing a wire from one component to another - this is referred to as physical connectivity.

You can also connect one pin to another by placing a short Wire and a Net Label on each component pin. The software identifies these two net sections and connects them to form a single net. This type of connectivity is referred to as logical connectivity.

Physical connectivity allows a user to follow each wire as they study the circuit, but a lot of wires can result in a dense and busy schematic. On the other hand, Net Labels reduce the amount of wiring, but the user must scan the sheet to find all potential connections. As the designer, you are free to decide which connectivity model best suits your design, including a mixture of both techniques.

Place wires to create physical connectivity or use net labels to create logical connectivity.

Place wires to create physical connectivity or use net labels to create logical connectivity.

As well as creating logical connectivity within a schematic sheet, there are also objects for creating logical connectivity between schematic sheets. The way this connectivity is created will depend on how you structure your schematic: either as a flat design or as a hierarchical design. More about this below.

There are a number of different net identifiers that can be used to connect between sheets.
There are a number of different net identifiers that can be used to connect between sheets.

Connectivity Insight 

The Altium NEXUS Connectivity Insight functionality (part of the Design Insight feature) displays an instant view of the connection relationships within a project. Shown as a document tree with optional schematic previews, the selectable elements provide a quick and visual way to navigate through a project's connectivity structure.

In its default setup condition, the Connectivity Insight feature displays:

  • The related net connection information when the cursor hovers over a schematic connectivity object (wire, port, etc.).
  • A tree-based connectivity preview map when Alt+Double-click is used on the object.

Adding to this capability is a feature that is accessed by hovering over an object that belongs to a signal net then pressing Ctrl+Alt. This opens a selectable tree view. Click the desired sheet in the tree to quickly jump to that document. 

This feature can be enabled/disabled on the System - Design Insight page of the Preferences dialog by checking/unchecking the Mouse Hover option for the Document Tree entry.

The net connectivity throughout a design can also be highlighted in all schematics by holding the Alt key when selecting a net by clicking on a wire (Alt+Click).

Objects Used to Create Connectivity

The schematic editor includes the following objects that are used to create connectivity. Collectively these objects are referred to as net identifiers.

Net Identifier Function
Bus Used to bundle a set of nets, for example, Data[0..7]. Nets must be named sequentially using a specific naming scheme (e.g., Data0, Data1,... Data7). This naming then dictates the Bus name, for example, Data[0..7].
Bus Entry Graphical device provided to support ripping two different nets from opposite sides of a bus line without creating a short between the two nets. Not required in other situations.
OffSheet Connector Used to connect a net from one schematic sheet to another sheet (not within the same sheet). Only supports horizontal connectivity (flat designs). OffSheet Connectors have limited functionality when compared to Ports.
Net Label A net identifier used to create connectivity to other Net Labels with the same name on the same schematic sheet. The net is automatically named by the Net Label. Net Labels can be placed on component pins, wires and buses. Note that Net Labels do not connect between sheets unless the project options are configured to use a Net Identifier Scope of Global.
Pin Pins are placed in the schematic symbol editor to represent the physical pins on the component. Only one end of the pin is electrically active, which is sometimes referred to as the hot end of the pin.
Port Used to connect a net from one schematic sheet to another. Connectivity can be vertical in a hierarchical design, or horizontal in a flat design (vertical and horizontal designs are explained below). Port names are used to name nets if the Allow Ports to Name Nets option is enabled in the Options tab of the Project Options dialog. in this situation, Ports will also connect within a schematic sheet.
Power Port Creates connectivity to every other power port of the same name, throughout the schematic project, regardless of the design structure. The net is automatically named by the Power Port. This net can be localized to a specific schematic sheet if required.
Sheet Entry Placed within a Sheet Symbol, to create connectivity to a Port of the same name on that Sheet Symbol's child sheet. Sheet Entries are used as net names if the Allow Sheet Entries to Name Nets option is enabled in the Options tab of the Project Options dialog.
Signal Harness Used to bundle any combination of nets, buses and lower-level signal harnesses.
Wire A polyline electrical design primitive that is used to form electrical connections between points on a schematic. A Wire is analogous to a physical wire.

Different types of net identifiers that have the same name do not automatically connect to each other. It depends on how the net naming options are configured. These options are discussed below.

How The Design Structure Affects the Connectivity

Related page: Multi-sheet & Hierarchical Designs

If the design does not fit onto a single schematic sheet, it can be spread over multiple sheets. There are two distinct models for organizing and creating connectivity in a multi-sheet schematic: either as a flat design, which you can think of as one large schematic sheet that has been cut up into a number of smaller sheets; or as a hierarchical design, where the sheets are linked in a grandparent-parent-child type structure.

Multi-sheet designs are implemented by placing a Sheet Symbol on the parent sheet, which represents and links to the child sheet, as shown in the image below.

Sheet Symbols represent (and link to) lower-level sheets. In a flat design, this structure can only be one level deep; in a hierarchical design, there is no limit to the depth.
Sheet Symbols represent (and link to) lower-level sheets. In a flat design, this structure can only be one level deep; in a hierarchical design, there is no limit to the depth.

So just what determines if a design is flat or hierarchical? This is done by setting the Net Identifier Scope to define how you want the sheet-to-sheet connectivity to be created. Set this in the Options tab of the Project Options dialog.

It is important to remember that for hierarchical designs, a project can contain only one top sheet. All other source documents must be referenced by sheet symbols. When performing a design validation, the Multiple Top Level Documents violation check can be used to flag if this is not the case. In addition, no sheet symbol may reference the sheet it's on or any sheet higher up the ladder, as this will create an irresolvable loop in the structure.

Flat Design

Related page: Multi-sheet & Hierarchical Designs

A design is referred to as a flat design when the connectivity is created directly from one sheet to another sheet. It does not pass through Sheet Symbols on the parent sheet. In a flat design, the sheet symbols simply represent (and reference) the child sheets. All sheets in the design appear at the same level in the Projects panel because there is no hierarchy. Both of the images below show a flat design.

Flat designs are simpler to create. A flat design can include a top sheet with a Sheet Symbol for each child sheet, but this is optional since this top sheet is not used to create sheet-to-sheet connectivity. For a small design that only has two or three schematic sheets in it, you might decide that a top sheet does not add any value. Once the sheet count gets higher, a top sheet can help the reader understand the functionality of the circuit design from the way that the logical blocks (Sheet Symbols) are arranged on the sheet.

The same design, shown without a top sheet (left) and with a top sheet (right) - both are examples of a flat design.  Projects panel showing a simple project that is a flat design, with a top sheet
The same design, shown without a top sheet (left) and with a top sheet (right) - both are examples of a flat design.

In a flat design, the connections between the sheets can be created by Ports, Offsheet Connectors, Power Ports, and Net Labels, as shown in the image above with the magnifying glass. The recommended approach is to use Net Labels within each sheet and Ports to connect between sheets. Ports offer more features than Off-Sheet Connectors, including the ability to add Port Cross References, which adds a SheetName[GridReference] to each port, referring to a matching port on another sheet, as shown in the image below.

There is no limit to the number of sheets in a flat design.

Port Cross References have been added next to each Port indicating the target sheet and grid reference for the matching Port.
Port Cross References have been added next to each Port indicating the target sheet and grid reference for the matching Port.

A design is flat when the connectivity is directly from one sheet to another. This connective behavior is defined by setting the Net Identifier Scope to Automatic, Flat or Global. Note that if you choose to use a mixture of Ports and Net Labels to create sheet-to-sheet connectivity, you cannot use the Automatic option. In this situation, you must manually set the Net Identifier Scope to Global.

Hierarchical Design

Main page: Multi-sheet & Hierarchical Designs

A design is referred to as hierarchical when the sheet-to-sheet connectivity is from a Sheet Symbol down to the child sheet referenced by that Sheet Symbol. At the net level, the connectivity is created between a Sheet Entry in that Sheet Symbol and a Port with the same name as the sheet entry on the child sheet. This type of connectivity is also referred to as vertical connectivity since the sheet-to-sheet connectivity that is created is only up and down between a parent sheet and its child sheet.

In a hierarchical design, the net-level connectivity is from a Sheet Entry on the parent sheet down to a matching Port on the child sheet.
In a hierarchical design, the net-level connectivity is from a Sheet Entry on the parent sheet down to a matching Port on the child sheet.

Hierarchical designs have two major strengths.

  1. The first is the ability to show the reader the functionality of the design in the way that the schematic sheets have been structured and presented as logical blocks (Sheet Symbols). The top-level schematic presents the design as a set of high-level functional blocks with the arrangement of the blocks reflecting their place in the traditional left-to-right, input-to-output flow of the overall circuit. These blocks can be further broken down into smaller blocks. if required, allowing the lowest level schematics that carry the components to have a relatively simple structure with a low component count. Because each sheet is relatively simple, the measured sheet size can be kept small, which is a big advantage when it comes to printing the schematic.
  2. The other major advantage is that it is generally much easier to trace a signal through a hierarchical design since the reader only needs to match a Sheet Entry on the parent sheet to the Port on the child sheet, and can trace the signal along the wiring within each sheet.

There is extra work in building up a hierarchical design. The Sheet Symbols require Sheet Entries and the top sheet must be wired to carry the signals from one Sheet Symbol to another. The software includes a tool to help keep the Sheet Entries synchronized with the child-sheet Ports (Design » Synchronize Sheet Entries and Ports for all Sheet Symbols, or right-click on a Sheet Symbol then choose Sheet Symbol Actions » Synchronize Sheet Entries and Ports for a single Sheet Symbol). It also includes tools to help break down a larger design into small chunks (Edit » Refactor » Move Selected Subcircuit to Different Sheet). To learn more about these restructuring and refactoring tools, refer to the  Design Refactoring page.

A hierarchical design can be any depth and include any number of schematic sheets.

A design is hierarchical when the sheet-to-sheet connectivity is only between Sheet Entries on the parent sheet and matching Ports on the child sheet. This connective behavior is defined by setting the Net Identifier Scope to Automatic, Hierarchical or Strict Hierarchical.

Multi-channel Design

Main article: Creating a Multi-channel Design

It is not unusual for an electronic design to include repeated sections of circuitry. It might be a stereo amplifier or a 64-channel mixing desk. This type of design is fully supported by a feature set known as multi-channel design. In a multi-channel design, you capture the repeated circuit once then instruct the software to repeat it by either placing multiple Sheet Symbols that all reference the same child schematic, or by configuring a single Sheet Symbol to repeat the referenced child schematic the required number of times. The compiled design is expanded out in the computer's memory with all components and connectivity repeated the required number of times in accordance with the user-defined naming scheme.

On the left, there are four Sheet Symbols all referencing the same child sheet (PortIO.SchDoc). On the right, the InputChannel.SchDoc is repeated eight times by the Repeat keyword.  An example of a multi-channel design where the child schematic is repeated by including the Repeat keword in its Sheet Symbol
On the left, there are four Sheet Symbols all referencing the same child sheet (PortIO.SchDoc). On the right, the InputChannel.SchDoc is repeated eight times by the Repeat keyword.

The logical design that you capture is never actually flattened; it always remains as a multi-channel schematic. When you transfer it to PCB layout the physical components and nets are stepped out the required number of times, and you have full access to the cross-probing and cross-selecting tools available for Working Between the Schematic and the Board. There is also a tool in the PCB editor to replicate the placement and routing of one channel across all other channels, with the ability to easily move and reorient an entire channel. Refer to the multi-channel design document to learn more about multi-channel design. 

A multi-channel design must be hierarchical because the software uses this structural model to instantiate the channels in memory.

For a multi-channel design, set the Net Identifier Scope to Automatic, Hierarchical or Strict Hierarchical.

The duplication of components and nets is resolved by the software using the naming scheme selected on the Multi-Channel tab of the Project Options dialog.

Setting the Net Identifier Scope

Dialog page: Options for Project

The software uses the current setting of the Net Identifier Scope to work out how to establish connectivity between the schematic sheets. The Net Identifier Scope is configured in the Options tab of the Project Options dialog (Project » Project Options).

Select the Net Identifier Scope mode to suit the structure of your design.
Select the Net Identifier Scope mode to suit the structure of your design.

The behavior of the Global, Flat and Hierarchical options are shown in the images below.

Simple examples of how connectivity is created for each of the three main modes: Global, Flat, Hierarchical. Configuring the Net Identifier Scope, example of what connects with the Flat option Configuring the Net Identifier Scope, example of what connects with the Hierarchical option
Simple examples of how connectivity is created for each of the three main modes: Global, Flat, Hierarchical.

As well as the three options mentioned above, there is also an Automatic option. Generally, it is better to leave the Net Identifier Scope set to Automatic. The software will select the most appropriate of the three options based on the structure of the sheets and the presence/lack of Ports and Sheet Entries.

When set to Automatic, the software automatically selects which of the three main net identifier modes to use based on the following criteria:

  • If there are sheet entries on the top sheet, Hierarchical is used.
  • If there are no sheet entries but there are ports present, Flat is used.
  • If there are no sheet entries and no ports, Global is used.

The Strict Hierarchical mode localizes all power ports to each sheet. In this mode, you must wire all the power and ground nets onto each child sheet using Ports and Sheet Entries. You can also do this for selective sheet(s) by not using the Strict Hierarchical mode, but still placing Sheet Entry(s) + Port(s) for the power net(s) you want to localize.

How Nets are Named

Each time you place a wire between component pins, you are creating connectivity. Every net in the design is given a name. If you have not placed a net identifier that can be used to name the net, the software names that net based on one of the pins in the net, for example, NetR7_1 as shown in the image below. If the component designator is changed at some stage, that system-generated net name is also changed and these changes must be passed between the schematic and PCB to keep everything in sync.

Nets without a net identifier are assigned a system-generated name based on one of the pins in the net.
Nets without a net identifier are assigned a system-generated name based on one of the pins in the net.

Net Labels always name the net to which they are attached. The default point of attachment is the bottom left corner of the Net Label, which is indicated by a small cross during movement.

For other net identifiers, they name the net if the appropriate option is enabled in the Netlist Options section of the Options tab of the Project Options dialog.

Different types of net identifiers do not automatically connect with each other. For example, a Port called Reset will not connect to a Net Label called Reset even if the Allow Ports to Name Nets option in the Project Options dialog is enabled. They must be connected by a wire. An example is shown in the images below.

  

Multiple Net Identifiers on a Net

You cannot have multiple Net Labels with different names on the same net within a schematic sheet. This situation will be detected and flagged as an error during validation. However, it is legitimate to have multiple net identifiers on a net on different sheets on which the net appears.

This ability allows you to:

  • Change the name of a net at different levels in the hierarchy to better reflect its function on that sheet.
  • Reuse a child schematic sheet without needing to rename nets on it.

The default setting is to assume that multiple net identifiers are not allowed. If they are detected during validation, a warning will be given. If you require them for your design, you will need to either:

  • Change the setting of the Nets with multiple names error check on the Error Reporting tab of the Project Options dialog or,
  • Suppress specific warnings by placing a No ERC Marker on each warning then choosing Specific Violations on the No ERC mode of the Properties panel to define the errors to suppress. Note that No ERC markers can be placed by right-clicking on a warning listed in the Messages panel or by right-clicking on the wavy colored line marking a violation on the schematic sheet. Their shape and color can be changed in the Properties panel when the No ERC marker is selected.

Options for Controlling the Naming of the Nets

Dialog page: Project Options

Ultimately, each net can have only one name on the PCB (one PCB net cannot have two names unless you are intentionally connecting two nets with a Net Tie). The software automatically resolves nets with multiple names to have only a single name in the project, but it may not be the name you expect. There are a number of options available to control how the name is chosen in the Netlist Options section of the Options tab of the Project Options dialog. Refer to the Project Options dialog page for more details about each of the options.

A good approach to setting these options is to enable the Allow Ports to Name Nets and the Higher Level Names Take Priority options. Combine these with sensible usage of Net Labels on significant nets on each sheet to ensure that all of the important nets, including those that traverse sheets, are named, and that the names assigned on the higher-level schematics are used on the lower-level schematics.

When there are multiple net naming options enabled, the precedence for naming nets is as follows:

  • If the Power Port Names Take Priority option is off, the order is Net Labels, Power Ports, Ports, Pins.
  • If the Power Port Names Take Priority option is on, the order is Power Ports, Net Labels, Ports, Pins.

Two Separate Nets That Have the Same Name

Another net naming issue that can arise is when the same net name has been used on different schematic sheets to label different nets. This will be detected during validation by the Duplicate Nets error check. You cannot transfer a design to the PCB with this condition present. Those two separate nets will be merged into a single PCB net during design transfer.

This situation can be resolved by enabling the Append Sheet Numbers to Local Nets option on the Options tab of the Project Options dialog. With this option enabled, all local nets have the value of the SheetNumber parameter appended to their name, as shown in the images below.

Example of how a duplicated net name, Input, appears on the schematic Editor tab  Example of how a duplicated net name, Input, appears on the schematic compiled tab
Since the net label Input has been used on multiple sheets, the Append Sheet Numbers to Local Net option has been enabled to prevent a Duplicate Nets error.
The effect of this can be seen by clicking on the complied sheet tab (right image), note that _2 has been appended to the net name.

The Append Sheet Numbers to Local Nets option will work only if each schematic sheet has been assigned a unique SheetNumber. The SheetNumber parameter is assigned on the Parameters tab of the Document Options mode of the Properties panel for each schematic sheet. As an alternative to manually assigning a unique number to each schematic sheet, run the Tools » Annotation » Number Schematic Sheets command, which opens the Sheet Numbering for Project dialog. This dialog can be used to assign unique SheetNumbers (a simple numeric value for each sheet) and DocumentNumbers (typically used for company-assigned document numbering) to all sheets.  

Intentionally Connecting Two Nets

There are situations when you need to intentionally connect two different nets. This is not a simple naming issue. It is when two nets need to be shorted as a design requirement. An example could be when you need to connect an Analog ground and a Digital ground in a controlled way.

This is achieved by connecting the two nets through a Net Tie component. A Net Tie component is nothing more than a controlled short circuit, allowing you to decide the location on the board where the nets connect. On the schematic, the Net Tie component has two or more pins, with each pin connected to one of the nets to be shorted. The Component Type property of the component is set to Net Tie, as shown below.

A Net Tie component being used to route a single clock to two FPGA clock pins on the schematic.
A Net Tie component being used to route a single clock to two FPGA clock pins on the schematic.

Note that the pins are not wired to each other on the schematic (they are not shorted on the schematic), but they are connected together within the PCB footprint.

On the PCB side, the footprint has the same number of pads as the schematic symbol has pins with copper between them. In the example image below, this is achieved by connecting two square pads with a length of track. This is done within the footprint in the PCB library editor. The PCB Component Type property is also set to Net Tie.

The software automatically ignores short circuits created within a Net Tie PCB component, therefore, a DRC error is not created.

The same Net Tie component on the PCB; the pads (selected) in the Net Tie footprint are shorted with a track.
The same Net Tie component on the PCB; the pads (selected) in the Net Tie footprint are shorted with a track.

When a Net Tie component is used to connect two different nets, each net retains its own name throughout the schematic and on the PCB.

  • When creating the Net Tie symbol and footprint, there are two Net Tie Component Type modes: one to include the Net Tie in the BOM (for example, if the Net Tie is a shorting jumper), the other to exclude it from the BOM (if the Net Tie is simply a length of copper) - select the required Component Type.
  • When routing the Net Tie on the board, any of the routing modes can be used to route away from a Net Tie pad. To route into a Net Tie pad, you must switch to the Ignore Obstacle mode.

Demonstration of routing a Net Tie component

Power Nets

The default behavior of the settings is to assume that power nets are global, i.e. you want them to be available on every schematic sheet. To access a power net, place a Power Port with the required net name then wire the components to that power port.

It's the net name that determines to which net a power port is connected, not the Style of the symbol - the three highlighted power ports all connect to the GND power net.
It's the net name that determines to which net a power port is connected, not the Style of the symbol - the three highlighted power ports all connect to the GND power net.

Localizing a Power Net - Globally

As mentioned previously, power nets can be localized to each schematic sheet in a hierarchical design by selecting the Strict Hierarchical option for the Net Identifier Scope. This approach localizes all power nets on every sheet, so they must be manually wired together, using the same approach as signal nets. If they are not wired together, there will be a Duplicate Net Name error for each power net present on each schematic sheet. You will also need to adjust the Connection Matrix settings to allow Ports to be connected to Power Ports.

If the Net Identifier Scope is set to Strict Hierarchical, 
If the Net Identifier Scope is set to Strict Hierarchicalevery power net must be wired to every sheet on which they are used.

Localizing a Power Net - Individually

A specific power net can also be localized on a specific sheet by wiring the Power Port to a Port on that schematic sheet.

Here the 3V3 power net has been localized for just this sheet, so it must also be manually wired on the parent sheet. The GND and 5V nets remain as global power nets.
Here the 3V3 power net has been localized for just this sheet, so it must also be manually wired on the parent sheet. The GND and 5V nets remain as global power nets.

Power Nets and Hidden Power Pins

Older versions of Altium's design software included features and options to support the use of hidden schematic component pins. This feature was useful when a design had a single power net and a single ground net, allowing all the power pins on all devices to be automatically connected to their respective nets by hiding those power pins. It was most popular on multi-part components, freeing you from having to display the power pins for these components on the schematic.  

Today, electronic designs typically have multiple power and ground nets. These nets are not simply routed to the relevant power pins; power delivery is now a critical aspect of successful board design. 

As the nature of designing power delivery networks has changed, the need to be able to hide component pins and have the software automatically connect them has dropped off to the point where most designers oppose this practice. Because of this, the software no longer supports defining a pin as hidden and pre-assigning its net name. Older projects that use this design approach will still netlist correctly when they are opened in the latest version of Altium's design software.

Dynamic Compilation

Related page: Verifying Your Design Project

When you connect two pins with a wire, you are drafting your design intentions, not creating an actual net. The net is not created until the project is compiled. As well as extracting details about the components and how they are connected, compiling also extracts detailed component and design parametric information. The compiled model of the project is referred to as the Unified Data Model.

In versions of the software prior to Altium NEXUS 3.0, the project had to be manually compiled to build the Unified Data Model. Since then, the design data model is incrementally updated after each user operation through dynamic compilation - creating what is referred to as the Dynamic Data Model (DDM). There is no manual compilation of the project involved, it is all done automatically. The design connectivity model is incrementally updated after each user operation, courtesy of dynamic compilation. For a design project, the automatic compilation process performs three functions:

  1. Instantiates the design hierarchy.
  2. Establishes net connectivity between all the design sheets.
  3. Builds an internal Dynamic Data Model (DDM) of the design.

This ensures that any design changes that are made are immediately reflected in the Navigator and Projects panel.

In order to check for logical, electrical, and drafting errors between the DDM and compiler settings, you must validate the project. This command is accessed by choosing the Project » Validate Project command from the main menus or by right-clicking over the entry for a project in the Projects panel, and choosing the Validate Project command from the context menu.  

Any violations that are detected by the Compiler will be listed as warnings and/or errors in the Messages panel. The Compiler uses the options defined on the Error Reporting and  Connection Matrix tabs of the Project Options dialog (as applicable to the project type), when checking the source documents for violations.

The Dynamic Data Model

A fundamental element of the software is the Unified Data Model (UDM). Data within the model can be accessed and manipulated by the various editors and services within the software including the schematic and the PCB. Rather than using a separate data store for each of the various design domains, the UDM is structured to accommodate all information from all aspects of the design, including the components and their connectivity. This single, cohesive model that sits central to the design process is created as a result of dynamic design compilation. It means that the Unified Data Model is available from the moment a project is opened and should not require additional manual compilation – a true Dynamic Data Model (DDM). Therefore, the model is incrementally updated (compiled) after each user operation. You can freely place, wire, rearrange, rename, add, and delete content from your schematic design.

The PCB design compilation process is managed by code outside of the schematic and PCB editors. There are a number of advantages to this approach, with the biggest being that the Unified Data Model of the design sits outside of the individual schematic and PCB editors. The UDM includes detailed descriptions of every component in the design and how they connect to each other.

The software manages the connective data across the schematic and the PCB.
The software manages the connective data across the schematic and the PCB.

The following locations and operations do not require any additional manual actions in terms of design compilation as compilation is dynamic:

  • Navigator and Projects panel
  • ActiveBOM
  • Performing ECO
  • Cross-probing
  • Net color highlighting
  • Pin swapping
  • Component cross reference
To automatically refresh the project view and Navigator panel after dynamic compilation, enable the Schematic.DynamicCompiler.Navigator.Autorefresh option in the Advanced Settings dialog (accessed by clicking Advanced on the System – General page of the Preferences dialog.

So how do you interact with the Unified Data Model, for example, to trace a net through the design? You do that through the Navigator panel.

Examining the Connectivity

Panel page: Navigator panel

If the design is large and spread over many sheets, it can become difficult to follow and verify the connectivity in the design. To help with this process, you can use the Navigator panel is used. The panel gives a view of the entire, compiled design. 

The basic approach to using the panel is to:

  • Set the browsing behavior by clicking the  Ellipsis button on the Navigator panel, click to configure the navigation preferences button at the top of the panel to open the Preferences dialog and enable your preferred Highlight Methods. Alternatively, right-click on the object of interest in the panel, and use the menu options to configure the navigation behavior, as shown in the image below.
  • Set the scope of your browsing in the Documents for region of the panel to browse the entire design select Flattened Hierarchy.
  • Click on a component in the Instance section of the list to jump to that component, expand the component to locate, or jump to a pin.
  • Click on a net or bus in the Net /Bus section to jump to that net or bus.
  • Hold the Alt key as you click to jump to that object on both the schematic and the PCB.

Click on a component or net in the Navigator panel to locate that component or net, and trace the connectivity through the design. Right-click to access display options. Hover the cursor over the image to show navigating to a component on the schematic and the PCB simultaneously (hold Alt as you click in the Navigator panel to include the PCB object).
Click on a component or net in the Navigator panel to locate that component or net, and trace the connectivity through the design. Right-click to access display options. Hover the cursor over the image to show navigating to a component on the schematic and the PCB simultaneously (hold Alt as you click in the Navigator panel to include the PCB object).

Navigating Components on the Board

As well as locating components on the schematic and the PCB (if Alt is held) from the Navigator panel, you can also navigate pins/components/nets/buses/harnesses on the PCB, directly from the schematic.

For example, as you click to locate a component on the schematic, you can also locate that same component on the PCB.

To do this:

  • Enable the Selecting option in the Highlight Methods, and also your preferred options in the Cross Select Mode section in the System - Navigation page of the Preferences dialog.
  • Enable Cross Selection (Tools » Cross Select Mode) in both the schematic and PCB editors.

These options configure the navigation and cross selection behavior.
These options configure the navigation and cross selection behavior.

Now as you select pins/components/nets/buses/harnesses on the schematic, those objects will also be selected on the PCB, as shown in the image below.

Selecting components and nets on the schematic, those objects are also selected on the PCB. Cross selection also works from the PCB to the schematic.
Selecting components and nets on the schematic, those objects are also selected on the PCB. Cross selection also works from the PCB to the schematic.

Cross Probing and Cross Selecting

As well as being able to select from one editor to the other (cross selection), the software also supports Cross Probing. Cross Probing has two modes, continuous (remain in the source editor) and jump-to (jump to the target editor). You can also cross probe from various panels and dialogs, for example, the Messages panel and the Engineering Change Order dialog. To learn more, refer to the Cross Probing and Selecting page.

Configuring the Color of Nets

Main page: Applying Color to the Nets

To help make the schematic more readable and make it easier to work with nets and routes in the PCB editor, color can be applied to schematic wiring, and the PCB nets and routes.

A highlight color can be applied to a net or a bus in the schematic editor using the commands in the View » Set Net Colors sub-menu, as shown in the image below. These colors can be transferred to the PCB editor at any time, via the Update PCB command.

In the PCB editor, the default color and visibility of the Connection Lines is configured in the System Colors section of the PCB View Configuration panel. Note that this default color is applied when the nets are created (during initial design transfer from schematic), the color of existing connection lines will not change if this option is changed.

In the PCB editor, the color applied to each net is displayed in the Nets mode of the PCB panel. Look for the color behind the checkbox next to the net name, as shown in the bottom right corner of the image below.

The color is always applied to the unrouted nets (connection lines). To display the color on the routed nets, enable the checkbox next to the net name in the PCB panel, and configure the display options in the Board Insight Color Overrides page of the Preferences dialog. In the image below, the override color Base Pattern is set to Solid, and the Zoom Out Behavior is set to Override Color Dominates.

The net colors applied in the schematic are transferred to the PCB by the Update PCB command. Configure the PCB Color Override features to control how they are displayed on the board.The net colors applied in the schematic are transferred to the PCB by the Update PCB command. Configure the PCB Color Override features to control how they are displayed on the board.

Press F5 to toggle the Net Color Override feature on / off, in both the schematic and PCB editors. You may need to also perform a screen refresh (End).

Changing the Color of the PCB Nets

It is not always possible to apply color to the schematic wiring and transfer it to the PCB. In this situation, color can still be applied to connection lines and routing in the PCB editor. To change the color of a net after the design has been transferred, double click on the net name in the Nets mode of the PCB panel. The color of an individual net can be edited in the Edit Net dialog.

To change the color of multiple nets, use the Nets mode of the PCB panel:

  • Use standard Windows multi-select techniques (Shift+click or Ctrl+click) to select multiple net classes or multiple individual nets.
  • Right-click on a selected object and choose the Change Net Color command from the context menu, to assign a new color to the selected nets.
  • Right-click a second time and choose Display Override » Selected On, to enable the color override feature for the selected nets.

Improve the visibility of nets by changing the color of their connection lines, and enabling the display override feature.
Improve the visibility of nets by changing the color of their connection lines, and enabling the display override feature.

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