Working with the Permitted Layers Design Rule on a PCB in Altium Designer

This document is no longer available beyond version 21. Information can now be found here: Permitted Layers Rule for version 24


Rule category: Placement

Rule classification: Unary


This rule specifies the layers on which components can be placed.

All design rules are created and managed within the PCB Rules and Constraints Editor dialog. For a high-level view of working with the design rules system, see Defining, Scoping & Managing PCB Design Rules.


Default constraints for the Permitted Layers rule.Default constraints for the Permitted Layers rule.

  • Permitted Layers - the layers permitted to be used when placing components. The following layer options are available:
    • Top Layer - allow component placement on the top layer.
    • Bottom Layer - allow component placement on the bottom layer.

How Duplicate Rule Contentions are Resolved

All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope expression matches the object(s) being checked.

Rule Application

Batch DRC.


The rule acts as a test when performing a Batch DRC, to ensure components - targeted by the query expression of the rule's scope - are being placed only on a permitted layer. Parameters specified for components on the schematic, and that have been brought across into footprints on the PCB, can be used to great effect for this very purpose. For example, to check that components that do not support wave soldering are not placed on the bottom layer, a rule of this type can be defined. If we consider a component parameter, SupportsWaveSolder, has been defined for components and brought across as parameters of the footprints in the PCB, then the rule scope might be:

CompParameterValue('SupportsWaveSolder') <> 'Yes'

and only the Top Layer constraint would be permitted, with the Bottom Layer constraint disabled.

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