Configuring and Running a Signal Integrity Analysis

When the design is prepared for a signal integrity analysis as required, configure and run the analysis itself as described on this page.

Configuring the SI Setup Options

When you select Tools » Signal Integrity and all components have models assigned, the SI Setup Options dialog displays the first time you run this command on an open project.

The SI Setup Options dialog
The SI Setup Options dialog

  1. Set the track impedance and average track length as required. These routing characteristics are only required if there are any nets not yet transferred to a PCB or unrouted nets in the PCB.

    Note that the Supply Nets and Stimulus tabs only display in schematic-only mode.
  2. Click on Analyze Design to run the initial default screening analysis and display the Signal Integrity panel from where you can further select the nets to analyze for reflection or crosstalk.

Four default tolerance rules and any Signal Integrity rules set in the schematic or PCB are all enabled and run the first time the design is analyzed. These tolerances can be set later in the Signal Integrity panel by clicking the Menu button and selecting Set Tolerances.

Signal Integrity Setup Options in Schematic Only Mode

If there is no PCB available in the project, you can change the SI setup options at any time by clicking the Menu button in the Signal Integrity panel and selecting Setup Options. The SI Setup Options dialog displays.

The Track Setup tab allows configuration of the default length of tracks when simulating. This is not used when a PCB is present as PCB uses width rules, i.e. if the Use Manhattan length option is disabled, PCB uses this value. Set the Track Impedance in this tab as well.

Click the Supply Nets and Stimulus tabs to display and enable net and stimulus rule information. These tabs allow another interface for defining these characteristics other than the normal method of providing rules on the PCB or schematic.

The tabs of the SI Setup Options dialog when accessed in schematic only mode
The tabs of the SI Setup Options dialog when accessed in schematic only mode

Using the Signal Integrity Panel

After performing any initial setup, the Signal Integrity panel will be loaded with data from the screening analysis that has just been run. The results of this analysis and a display of which nets have passed the various tests are displayed in the list on the left-hand side of the panel. The problematic nets can then be analyzed in greater detail by running fast reflection and crosstalk analyses. The ability to add virtual terminations allows you to ascertain what additional circuitry need be added to the design to resolve these problem areas and hence obtain the most efficient signal integrity performance.

The Signal Integrity panel is used to configure and control the signal integrity analysis process.
The Signal Integrity panel is used to configure and control the signal integrity analysis process.

  • Note that there is only one copy of this panel in the system so running Tools » Signal Integrity again will clear the existing panel and reload it with a new set of results. This may be used to refresh the results after making changes to either the PCB or schematic documents in the project or when starting to analyze a new project.
  • The Reanalyze Design button allows you to perform the screening analysis again for the current design and should be used if you have made any changes to the design documents. In this way, you are assured of having the most up-to-date results for your design. You do not need to reanalyze the design after adding/editing signal integrity design rules as the screening results are compared against the enabled rule tolerances in real time.

Viewing the Screening Results

The initial screening analysis provides a fast simulation of many nets to enable you to get more information and identify critical nets for closer examination, such as detailed reflection and/or crosstalk analysis. The left-hand side list displays the results of this analysis. in tabular format. For each net in the design, the following column information can be displayed:

Net

The net name and a graphical representation of its status. This column is permanently displayed.

Status

A textual representation of the net's screening analysis status. This column is displayed by default.

Analysis Errors

Information as to why a net can't be analyzed.

Base Value

The voltage that the signal on the net settles to in the low state.

Falling Edge Flight Time

The time it takes for the signal on the net to fall to the threshold voltage, less the time it would take for a reference load (connected directly to the output) to fall to the threshold voltage.

Falling Edge Overshoot

The maximum overshoot (ringing below the base value) on the falling edge of the signal. This column is displayed by default.

Falling Edge Slope

The time it takes for the signal on the net to fall from the threshold voltage (VT), to a valid low (VIL).

Falling Edge Undershoot

The maximum undershoot (ringing above the base value) on the falling edge of the signal. This column is displayed by default.

Length

The total net length (sum of all routed track segments in the net).

Impedance

The average impedance for the net (in Ohms). This is the average of the impedance of each track segment, weighted by its length.

Rising Edge Flight Time

The time it takes to drive the signal on the net to the threshold voltage, less the time it would take to drive a reference load (connected directly to the output) to the threshold voltage.

Rising Edge Overshoot

The maximum overshoot (ringing above the top value) on the rising edge of the signal. This column is displayed by default.

Rising Edge Slope

The time it takes for the signal on the net to rise from the threshold voltage (VT), to a valid high (VIH).

Rising Edge Undershoot

The maximum undershoot (ringing below the top value) on the rising edge of the signal. This column is displayed by default.

Routed

Shows whether the net is routed (full or partial) in the design (True) or totally unrouted (False).

Top Value

The voltage that the signal on the net settles to in the high state.

Use the Menu button or right-click in the table to access the Show/Hide Columns sub-menu, from where you can enable/disable the display of data columns as required.

Each net can be in one of three categories: Passed, Failed or Not Analyzed.

 A Passed net had all values inside the bounds defined by the tests.
A Failed net had at least one value outside the defined tolerance levels. Any values that are failed are colored in yellow.
A Not Analyzed net could not be screened for some reason. To view the reason, enable the Analysis Errors column.

Failed Nets

Common reasons for a failure to analyze a net in screening include containing a connector, diode or transistor, and no output pins or multiple output pins. When nets are screened which contain bi-directional pins and there is no dedicated output pin in the net, each bi-directional pin is simulated separately as an output pin. The worst-case result from these simulations is displayed.

Note that even though a net could not be analyzed for screening, it may still be able to be checked in reflection and crosstalk simulations. For a net containing a connector, you can simulate the connector using an equivalent impedance model added to this net.

It is possible for nets to have other errors that will lead to incorrect analysis results in both screening and further simulations. These nets will appear with their entire row entry colored in red. Also, nets that have been simulated (i.e. nets that are not yet routed on a PCB) are colored in light gray.

Checking Failed or Not Analyzed Nets

To view the cause of a Failed or Not Analyzed net:

  • If the entire row of a net is highlighted in red, select it and then right-click and select Show Errors. This also adds messages to the Messages panel, which can be cross-probed to repair any issues.

  • To view all available information for a selected net, right-click and select Details. The Full Details dialog shows all of the screening analysis results that can be displayed in the results table, along with the following:
    • Component Count – how many components have pads that connect to the selected net.
    • Track Count – how many individual routed track segments comprise the total routed net.
    • Minimum Impedance (Ohms) – the minimum impedance for the net, considering the individual impedances of all track segments in the net.
    • Maximum Impedance (Ohms) – the maximum impedance for the net, considering the individual impedances of all track segments in the net.

  • Select Cross Probe from the right-click menu (or click Menu) to cross probe to the selected net on either the schematic or the PCB.

    Use the F4 shortcut key to toggle display of the Signal Integrity panel (and other panels that are currently in 'floating' mode) to quickly switch between the panel and your design.
  • Display which nets are coupled to either a single net or a group of nets by selecting the desired nets and then right-clicking and selecting Find Coupled Nets. This will select all nets that are coupled to these selected nets. The criteria for which nets are considered coupled can be configured in the Signal Integrity Preferences dialog (accessed by clicking the Menu button and selecting Preferences in the Signal Integrity panel).
  • Useful information can be copied to the clipboard and pasted into other applications for further processing or reporting. Select the nets required and choose Copy from the right-click menu. Additionally, the displayed information can be customized by selecting which columns will be shown using the Show/Hide Columns command from the right-click menu.
  • A report highlighting the results generated by the analysis is also available by selecting Display Report from the right-click menu in the Signal Integrity panel. This opens the report file Signal Integrity Tests Report.txt in the Text Editor and adds it to the project.

Setting Preferences

You can specify various preferences that apply to all the analyses that you have defined. These include general settings, integration method and accuracy thresholds. Any changes made to the preferences will apply to all projects.

Click the Menu button in the Signal Integrity panel and select Preferences to open the Signal Integrity Preferences dialog.

The Signal Integrity Preferences dialog
The Signal Integrity Preferences dialog

All Signal Integrity preferences can be returned to their defaults by clicking on the Defaults button in the dialog.
  • Use the General tab to set the error handling options that show hints and/or warnings when errors exist in the design that relate to performing a Signal Integrity analysis. Any hints or warnings encountered will be listed as messages in the Messages panel. If the Show Warnings option is enabled and warnings exist, a warning confirmation dialog will appear when trying to access the Signal Integrity panel. Additionally, you can opt to hide the Signal Integrity panel after choosing to display waveforms. You can also define the default units for Signal Integrity measurements, whether plot titles and FFT charts will be displayed when the resulting waveforms are shown in the SimData editor.
  • The Configuration tab defines various simulation-related thresholds, such as the maximum distance between coupled nets and the minimum length to be considered a coupled section.
  • The Integration tab defines the numerical integration method used for analysis. The Trapezoidal method is relatively fast and accurate but tends to oscillate under certain conditions. The Gear methods require longer analysis times but tend to be more stable. Using a higher Gear order theoretically leads to more accurate results, but increases analysis time. The default is Trapezoidal.
  • The Accuracy tab in the Signal Integrity Preferences dialog defines tolerance thresholds and limit settings for various computational algorithms involved in the analysis.
  • Use the DC Analysis tab to define tolerance thresholds and limit settings for various parameters associated with DC Analysis.

Setting Tolerances

Default overshoot and undershoot tests are defined as these are probably the best characteristics to use in determining which nets may be the most problematic. Four default tolerance rules and any Signal Integrity rules set in the schematic or PCB are all enabled and run the first time the design is analyzed. To enable or disable these rules, click on the Menu button in the Signal Integrity panel and select Set Tolerances. The Set Screening Analysis Tolerances dialog displays.

The Set Screening Analysis Tolerances dialog
The Set Screening Analysis Tolerances dialog

Click on the Enabled checkbox next to a rule type to enable that rule to run when the design is analyzed.

Click on PCB Signal Integrity Rules (if not in schematic only mode) to open the PCB Rules and Constraints Editor dialog where you can add or modify any Signal Integrity rules required. Click OK until you return to the Signal Integrity panel.

Preparing Analyses

Before running the analyses, the nets to further analyze must be selected. You can also edit buffers to view or change the component part technology and pin properties and add terminations to nets if required.

Selecting Nets to Analyze

To perform further analysis on nets (reflection and/or crosstalk) the nets must be selected in the right-hand list of the Signal Integrity panel. Double-click on a net in the left-hand list to select it and move it to the right-hand list. Alternatively, use the arrow buttons to move nets to and from this selected state. You can multi-select nets in the left-hand list by holding down the Shift or Ctrl keys.

You can cross probe to the selected net(s) on the relevant schematic or PCB document by selecting the Cross Probe options from the right-click menu. The target document will be made active in the design space and the selected net(s) will be displayed in accordance with the highlighting methods defined on the System – Navigation page of the Preferences dialog.

Once nets are in this selected state, it is possible to perform further configuration for them before running a simulation.

Setting Victim and Aggressor Nets

In the case of Crosstalk analyses, it is necessary to set a victim or an aggressor net. Note that due to the nature of the analysis, this functionality is only available when two or more nets have been selected (moved to the right-hand list).

Select a net in the right-hand list of nets, right-click and select Set Aggressor or Set Victim as required. The status of the nets is updated. To unset the nets, select Clear Status from the right-click menu.

Setting the Direction of Bidirectional Pins

It is possible to set the direction of bidirectional pins in a given net. To set the direction, select the affected net in the top right-hand list. This will then display a list of pins for that net below. From the list of pins, change the in/out status for each selected bidirectional pin by right-clicking and choosing a status from the right-click menu. These in/out settings will be saved with the project for the next time you use this panel.

You can also cross probe to the pin/pad on the relevant schematic or PCB document by selecting the Cross Probe options from the right-click menu. The target document will be made active in the design space and the selected pin/pad will be displayed in accordance with the highlighting methods defined on the System – Navigation page of the Preferences dialog.

Editing Buffers

You may wish to view or change the component part technology and pin properties, such as input and output models and pin direction. You can only modify components that are attached to the currently selected net in the right-hand list. Using the Edit Buffer option under the right-click menu in the list of pins, gives access to the component's data dialog.

The dialog and options that appear will depend on the type of component the pin belongs to, e.g. resistor, IC, BJT, etc. The Integrated Circuit dialog shown is for an IC component type.

The Integrated Circuit dialog
The Integrated Circuit dialog

Choosing a pin Technology and Direction will display a list of relevant input and/or output models to select from. Changes to the technology and direction are used locally in the analysis only and these will not be saved when the panel is reset.

The part Technology, Input Model and Output Model fields are context-sensitive. When you choose a component part technology, the default models of the part are taken from this technology. Note that if specific pin models have already been assigned (for example as part of importing an IBIS model), changing the component part technology will not re-assign pin models for those pins.

Note that you are really editing the properties of a pin rather than the whole component, even though you can change the component's technology. Any changes you make using the Edit Buffer command (or by double-clicking on a pin) will override any technology/pin model setup created when you set up the Signal Integrity model in the schematic.

Note that changes made using this approach are NOT retained between analysis sessions, the idea is that this feature is used to quickly change the assigned pin model to test what-if scenarios. If you want the assignments to be retained, edit the models assigned to the component instead of editing the pin models.

Terminations

The oscillations apparent on a signal waveform are due to multiple reflections on the associated transmission line (trace). These reflections, or 'ringing', occur most often in PCB designs because of driver/receiver impedance mismatch – usually where there is a low impedance driver and a high impedance receiver.

Getting good signal quality at the load would ideally mean zero reflections (no ringing). The level of ringing can be reduced to an acceptable level for the design using a termination.

The Signal Integrity panel incorporates a termination advisor, which enables you to insert 'virtual terminations' into a net at a location you define. In this way, you are free to test various termination strategies, without making physical changes to your board.

Termination simulations available are:

  • Series Res
  • Parallel Res to VCC
  • Parallel Res to GND
  • Parallel Res to VCC and GND
  • Res and Cap to GND
  • Parallel and Cap to GND
  • Parallel Schottky Diodes

Each termination type can be enabled or disabled in the termination list. Multiple termination types can be enabled when performing reflection and crosstalk analyses - a separate set of waveforms will be produced for each. This allows you to determine the best termination to add to the design to achieve optimal signal quality on transmission lines and therefore reduce reflections (ringing) to an acceptable level.

When a reflection or crosstalk analysis is run, each enabled termination type will be tried and produce a separate set of waveforms. When the Serial Res termination is used, it will be placed on all output pins in the selected net. For other termination types, the termination will be placed on all input pins in the net.

To achieve the best results for the terminations, it will also be necessary to set the value of the parts involved based on the characteristics of the net.

  • When a termination is selected, a diagram showing that termination is displayed below. This diagram will allow the setting of both minimum and maximum values for the resistors and capacitors used in the terminations.
  • Minimum and maximum values are used when the sweep count (shown in the list of terminations) is set to a number greater than one.
  • For more information about a termination type, select it and click the ? (Help) button. If you enable the Suggest option, suggested values will be calculated (according to the formula noted in the information popup for each termination type) and displayed in gray. You can accept these values or disable the Suggest option and enter your own values as required.
  • If you want to run the analysis with a swept range of values for the termination components, ensure that the Perform Sweep option is enabled and set the number of Sweep Steps required when the analyses are run. The values used at each sweep of the analysis will depend on the minimum and maximum values entered and the value chosen in the Sweep Steps field (e.g., if Sweep Steps is set to 2, the first pass of the analysis will use the minimum value and the second the maximum). Note that a separate set of waveforms will be generated for each sweep for comparison purposes.

Placing a Termination on the Schematic

Once the waveforms have been created and the optimum termination detected, it may be desirable to place that termination directly on the schematic sheet. This can be achieved via the right-click menu in the Termination list. Note that any placement will only apply to the currently selected net.

If you wish to actually place the selected termination circuit on the schematic rather than just use it as a 'virtual termination':

  1. Right-click in the Termination section of the Signal Integrity panel and select Place on Schematic.
  2. The Place Termination dialog displays, allowing the setting of various properties such as which library components to use for the termination parts, whether to use automatic or manual placement, whether to place on all applicable pins or just the selected pin and the exact values to be used for the parts. Click OK to continue.

    The Place Termination dialog
    The Place Termination dialog

  3. The Signal Integrity Analyzer finds the source schematic document that the pin belongs to. Then, in a free space on the document, it will add the necessary parts with the correct values (resistors, capacitors or whatever is required) and the power objects. Connect this termination circuit to the appropriate pin in the schematic.

Note that it will still probably be necessary after this to wire the components correctly to the pin. Additionally, if there is a PCB involved as well, these will need to be synchronized and routed in the PCB. Synchronize the PCB to add these parts as well by selecting Design » Update PCB.

Running the Analyses

Once the nets have been configured as necessary (and any termination options chosen), click the Reflections or the Crosstalks button in the Signal Integrity panel to generate the waveforms.

  • For a Reflection analysis, one or more nets can be simulated. The number should be kept to a reasonable amount however, as analysis time will increase considerably when analyzing high numbers of nets.

    The Signal Integrity Analyzer calculates voltages at nodes of a net using routing and layer information from the PCB and associated driver and receiver I/O buffer models. A 2D-field solver automatically calculates the electrical characterization of the transmission lines. Modeling assumes that DC path losses are small enough to be ignored.

  • For a Crosstalk analysis, at least two nets must be taken over. Two or three nets would normally be considered at any one time when performing a crosstalk analysis, usually a net and its two immediate neighbors.

    The level of crosstalk (or the extent of EMI) is directly proportional to the reflections on a signal line. If the signal quality conditions are achieved and reflections are brought down to a near-negligible level through correct signal termination, i.e. the signal is delivered to its destination with minimal signal stray and crosstalk will also be minimized. See Terminations for more information.

    Crosstalk analysis is only possible when performing post-layout signal integrity analysis from a PCB design document. This is because routed nets are required for this type of analysis.

After clicking a button, the analysis commences and a simulation data file (<ProjectName>.sdf) is generated. This file opens as a separate tab, displaying the results of the analyses in the SimData editor.

Refer to the Working with Signal Integrity Analysis Results to learn more.

Note

The features available depend on your level of Altium Designer Software Subscription.

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