BOM CoDesign

The 3D MID DRC Check feature provides batch design rule checking for routed tracks on 3D substrates, ensuring that Width, Clearance, Length, and Matched Length requirements are all validated against the design. By automatically identifying rule violations across the full 3D geometry, this capability helps to maintain accuracy, prevent manufacturing issues, and confirm that complex 3D routing meets all defined constraints before moving forward.

ODB++ Intellectual Property Protection

Available in Closed Beta

The Altium Beta Program offers every Altium software user the opportunity to gain early access to new Altium Design features.

ODB++ Intellectual Property Protection provides precise control over which parts of a design are included in the ODB++ output, ensuring that each fabrication or assembly partner receives only the information required for their portion of the manufacturing process. The feature allows teams to selectively export signal layers, choose whether the netlist is included, disabled, or neutralized, and control how components are represented, including the ability to remove component data entirely or export components without their properties. By tailoring the level of information shared for each vendor, this capability supports a wide range of IP protection needs and keeps sensitive design details safeguarded while still delivering the essential data needed to build the board.

Enhanced Design Reuse Panel

Available in Closed Beta

The Altium Beta Program offers every Altium software user the opportunity to gain early access to new Altium Design features.

The enhanced Design Reuse panel provides a clearer, more intuitive way to work with reuse blocks and snippets, making it easier to incorporate proven design elements into new projects. The updated panel offers improved organization and navigation, giving faster access to reusable content and helping to maintain consistency, reduce repeated effort, and accelerate development by confidently reusing validated circuitry.

Embedded 3D Models for Harness Designs feature automatically embeds Parasolid-format 3D models into harness layout drawings. These models are generated when adding a Physical View for a harness component or connection point, and any existing but unembedded models are incorporated upon saving the layout drawing. This enhances integration with MCAD CoDesigner, facilitating seamless synchronization between electrical and mechanical design domains. 

Export 3D-MID Tracks as Centerline Curves

Available in Closed Beta

The Altium Beta Program offers every Altium software user the opportunity to gain early access to new Altium Design features.

3D-MID Export of Tracks to Centerline Curves enables the export of conductive tracks on a 3D substrate as precise centerline curves within STEP files, supporting advanced 5-axis manufacturing processes. This achieves more accurate representations of conductive pathways, facilitating seamless integration with mechanical CAD tools and enhancing the precision of manufacturing processes. 

3D Automatic Face Filling

Available in Closed Beta

The Altium Beta Program offers every Altium software user the opportunity to gain early access to new Altium Design features.

3D Automatic Face Filling automatically generates a geometric pattern to fill a face of a substrate in 3D-MID designs, based on selected tracks. It creates a patterned covering that extends perpendicular to the track, adapting to surface boundaries and avoiding obstacles. This provides a faster and more efficient way to create protective meshes for security purposes, such as in secure payment terminals, without the need for manual routing.

Z-Axis Clearance Rule

Available in Closed Beta

The Altium Beta Program offers every Altium software user the opportunity to gain early access to new Altium Design features.

The Z-Axis Clearance Rule checks the shortest distance between copper features across different layers in a PCB design. It is available in both the Constraint Manager and the legacy PCB Rules Editor. This rule enables precise layer-to-layer clearance checks for specific net classes, differential pairs, or through schematic parameter directives. It supports both Online and Batch Design Rule Checks (DRC), integrates with polygon pours and PCB CoDesign, and includes optional in-PCB violation overlays for clear visualization of rule breaches.

Advanced Polygon Pour Engine

Available in Closed Beta

The Altium Beta Program offers every Altium software user the opportunity to gain early access to new Altium Design features.

Supports true arcs rather than relying on approximated curves during copper pours. This upgraded engine is a substantial improvement to the polygon pour process in Altium Designer. By rendering arcs natively, it delivers smoother and more precise copper shapes, significantly improving visual quality and ensuring cleaner, more professional PCB designs. Additionally, users benefit from faster repour times, streamlining design iterations and boosting overall performance during layout edits.

Sawtooth Rounding Support for Length Tuning

Available in Closed Beta

The Altium Beta Program offers every Altium software user the opportunity to gain early access to new Altium Design features.

Sawtooth Rounding for Length Tuning enhances the precision of your signal routing by enabling corner rounding on sawtooth patterns during Interactive Length Tuning or within-pair matching in the Auto Tuning process. This feature introduces adjustable rounding levels from 0% to 50% in 5% increments. By smoothing sharp corners in tuned traces, it helps maintain consistent impedance and improve signal integrity—especially critical in high-speed digital designs.

Solder Mask Zero Expansion is a move toward industry alignment, specifically with IPC-7351B and IPC-2581B standards. This changes the default solder mask expansion value from 4 mil to 0 mil.

Support for Increased Signal Layers

Available in Closed Beta

The Altium Beta Program offers every Altium software user the opportunity to gain early access to new Altium Design features.

Increases the number of signal layers available in Altium Designer from the current limit of 32 up to 128. This allows the design of more complex, high-density PCBs, enhancing the ability to handle larger, more sophisticated projects with greater ease and flexibility. Additionally, this enhancement will extend to Allegro and Xpedition importers to enable smooth and accurate importing of PCB designs exceeding 32 signal layers.

Dynamic Re-route on Component Drag

Available in Closed Beta

The Altium Beta Program offers every Altium software user the opportunity to gain early access to new Altium Design features.

Dynamic Re-route on Component Drag allows components to dynamically re-route during movement and placement, with configurable limits on the number of connections to optimize performance. This feature streamlines the design process, reduces manual rework, and minimizes errors, leading to faster development cycles and improved overall design quality.

The 3D layout tool for Mechatronic Integrated Device (MID) designs seamlessly merges electronic and mechanical elements, opening up possibilities in diverse fields like wearables, medical devices, and automotive components. The tool simplifies the 3D design process with easy integration, synchronized design, logic-driven layout, and precise placement. It also ensures production-ready data export. The tool is user-friendly, eliminating the need for complex workarounds and making it suitable for the entire 3D-MID design process.

Unified Login allows signing in to an Altium Account through an external browser using various methods, including direct email credentials, linked Facebook or Google accounts, or Single Sign-On (SSO). This feature is a streamlined login mechanism integrated with Altium Designer for easy account access.

Static Phase Matching enables the static alignment of differential pair lengths as part of the automatic differential pair length tuning process. This feature is crucial for maintaining the integrity of high-speed signal transmissions across PCB layouts.

The Simulation S-parameters (scattering parameters) tool facilitates an approach for describing networks based on the ratio of incident and reflected microwaves. These ratios can be subsequently used to calculate the properties of a circuit including input impedance, frequency response and isolation. While this type of analysis is primarily for RF circuits and components, it is equally useful for any circuit with at least two sources (ports). Using S-parameter data as a tool to optimize your design can lead to cost savings, improved product quality, and a competitive edge in the marketplace.

The Stress Analysis simulation tool computes critical operating conditions like maximum voltages, currents, and power dissipation for components. It examines these conditions against predefined limits specified in a component's stress model, allowing for early identification of potential points of failure. This precision supports the selection of robust components, enhances design efficiency, and minimizes the risk of costly failures, contributing to improved overall design quality and reliability.