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Parent category: Violations Associated with Nets
Default report mode:
This violation occurs when there are two or more hidden pins within the project that have the same value entered into their Hidden Net Name property. Hidden pins are sometimes used to define the power pins in a multi-part component. Typically this warning occurs when a library component with hidden pins has been used and the designer was not aware of those hidden pins.
If compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic - Compiler page of the Preferences dialog), an offending object will display a colored squiggle beneath it. Hovering over the object will display a pop-up hint that summarizes the violation. A notification is also displayed in the Messages panel in the following format:
Adding hidden net
The problem arises when the following properties for the offending pin(s) occur:
If it is by design then the warning can be ignored. Alternatively you can enable the display of the pin(s) in the workspace. This option may prove to be less than desirable, especially if you have many hidden pins connected to power nets. Revealing these pins in the workspace can cause clutter as each pin would need to be wired to the appropriate power port object - making the design schematic(s) less easy to read.
If you choose to display the hidden pins and those pins are assigned to Part Zero, they will appear on every part placed in the project. For multi-part component power pins that are not hidden, it can be better to create a separate part in the component just for the power pins.
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