Что нового в Altium Designer

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This page details the improvements included in the initial release of Altium Designer 24, as well as those added in subsequent updates. Along with delivering a range of improvements that develop and mature the existing technologies, each update also incorporates a large number of fixes and enhancements across the software based on feedback raised by customers through the AltiumLive Community's BugCrunch system, helping you continue to create cutting-edge electronics technology.

You can choose to continue with your current version, update your current version, or install Altium Designer 24 alongside your current version to access the latest features. Your current version can be updated from within the software in the Extensions and Updates view. If you prefer to install Altium Designer 24 alongside your current version, visit the Altium Downloads page to download the installer, then choose New Installation on the Installation Mode page of the installer.

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Altium Designer 24.7

Released: 23 July 2024 – Version 24.7.2 (build 38)

Release Notes for Altium Designer

Schematic Capture Improvements

Enhancement to Multi-part Components

If a multi-part component only has primitives defined in one sub-part, the designator suffix is now hidden when that sub-part is placed on a schematic sheet. This is only for alternate display modes; the suffix is always shown for the Normal display mode. Also, it is no longer possible to select a sub-part (or alternate display mode) when that sub-part/mode has no primitives.

Javascript ID: MiltiPart_DisplayModes_Properties

An example of a schematic symbol of a dual op amp component. The normal mode represents the component in two sub-parts. An alternate mode represents the component as a single sub-part.

On the schematic sheet, the designator suffix is not shown for the sub-part when it is the only sub-part in the selected alternate mode.

It is no longer possible to select a sub-part when that sub-part has no primitives.

It is no longer possible to select a alternate display mode when that mode has no primitives.

For more information, refer to the Creating a Schematic Symbol page.

Added New Port Violation

A new violation type has been added to the Violations Associated with Nets category on the Project Options dialog's Error Reporting tab to detect a flat design port that does not have a corresponding/matching port in any source schematic documents. The Port with no matching ports error violation will occur when there is no matching port, or a port is not connected. The default status of the violation is No Report.

This violation type will only be detected if the Net Identifier Scope option on the Options tab of the Project Options dialog is set to either Flat (Only ports global) or Global (Netlabels and ports global).

For more information, refer to the Verifying Your Design Project page.

Ability to Keep Symbol/Footprint Unchanged for Alternate Parts

You can now choose an alternate part with no changes to a symbol on a schematic or needing to add a footprint to the PCB. In the Properties panel, enable the Do not overwrite schematic symbol and/or Do not overwrite PCB footprint options as needed, as shown in the image below. Parameters for the chosen alternate are faithfully presented in the ActiveBOM.

For more information, refer to the Working with the Variant Manager page.

PCB Design Improvements

Added Additional Options to Layer Stack Manager

Parameters have been added to the Layer Stack Manager Properties panel for a few key parameters that are important for Power Integrity simulation. Copper Resistance and Via Plating Thickness can be defined using the Properties panel as part of the properties for a board’s layer stack.

These parameters are included when exporting the board into Ansys EDB format. The Power Analyzer by Keysight tool also supports the Via Plating Thickness parameter. The value of this parameter is displayed in the Configuration region of the analyzer document.

For more information, refer to the Defining the Layer Stack page.

Return Path Via Check (Open Beta)

When a high-speed signal passes from one reference plane to another, there should also be return vias to pass the return signals between the planes. In order to check if such a via exists within a specific distance from a signal via, the Return Path rule has been extended with a new Max Stitch Via Distance option with which you can define if a return path via should be present within a given distance (a default value is 1.5mm) from a via of the scoped signal. The return path via should provide connection to the reference layer defined in Layer Stack Manager for the corresponding impedance profile.

An example of the max stitch via distance constraint configured in the Constraint Manager
An example of the max stitch via distance constraint configured in the Constraint Manager

An example of the max stitch via distance constraint configured in the PCB Rules and Constraints Editor dialog
An example of the max stitch via distance constraint configured in the PCB Rules and Constraints Editor dialog

When the Max Stitch Via Distance option is enabled in the rule and a non-zero value is defined for it, the presence of a return path via within the specified distance is checked as part of the Batch DRC.

An example of the max stitch via distance constraint violation. Here, a via of net DQS4R_N has no return path via at the specified distance.
An example of the max stitch via distance constraint violation. Here, a via of net DQS4R_N has no return path via at the specified distance.

This feature is in Open Beta and available when the PCB.Rules.CheckReturnPathVia option is enabled in the Advanced Settings dialog.

For more information, refer to the High Speed Design page.

Enhanced Trace Loop Removal (Open Beta)

 
 
 
 
 

Introduced a new implementation of automatic loop removal in the Interactive Router. This update improves behavior when using the loop removal functionality when routing using the Any Angle corner style, improves behavior of via removal after loop removal (see below), and lays the foundation for future enhancements.

Remove Via After Loop Removal

When there is a direct via-to-pad connection, the via will now be removed if deemed no longer needed after loop removal (provided the Remove Loops With Vias option is enabled in the Properties panel for interactive routing).

This feature is in Open Beta and available when the Legacy.PCB.Routing.LoopRemoval option is disabled in the Advanced Settings dialog.

For more information, refer to the Interactive Routing and Differential Pair Routing pages.

PCB CoDesign Improvement

Added Ability to Leave Feedback to Altium

A Leave Feedback control has been added to the PCB CoDesign panel, allowing you to send feedback directly to Altium Developers with suggestions or issues related only to the PCB CoDesign feature.

For more information, refer to the PCB CoDesign page.

Constraint Manager Improvements

Import/Export of Constraint Sets between Designs

This feature allows you to import and export constraint sets, which enables you to quickly reuse constraint information between different board designs. To access this new feature, right-click in the Clearances, Physical, or Electrical view of the Constraint Manager, then select Export Constraint Sets or Import Constraint Sets.

Exporting Constraint Sets

After selecting Export Constraint Sets, the Constraint Sets for Export dialog opens with all constraint sets that are currently present in the design listed in the grid. Select the constraint sets you want to export using checkboxes, then click OK. The selected constraint sets will be exported into a file with the extension *.CstrDot. The file can then be imported into another design.

Importing Constraint Sets

After selecting Import Constraint Sets, the standard File Explorer dialog opens in which you can select a *.CstrDot file to import. In the Constraint Sets for Import dialog that opens, select the constraint sets you want to import from the file, then click OK. Imported constraint sets can be inspected in the Properties panel when the corresponding view of the Constraint Manager is selected and can be applied to objects.

For more information, refer to the Defining Design Requirements Using the Constraint Manager page.

Global Option to Ignore Pad-to-Pad Clearance within Footprint

A new global option allows you to specify whether clearances between pads in the same component footprint are ignored. The option is available from the Clearances and Physical views when the Constraint Manager is accessed from either the schematic or PCB. Toggle the Ignore Pad to Pad clearances within a footprint option in the Clearances Settings region of the Properties panel to apply the setting to all defined clearance rules.

For more information, refer to the Defining Design Requirements Using the Constraint Manager page.

Harness Design Improvements

Display Options for Cavities in Connection Table

You now have the ability to control the type of cavities that are displayed in a Connection Table of a Harness Manufacturing document (*.HarDwf). Use the Display drop-down in the Properties panel to select the desired cavities to be displayed:

  • Wires Only – show only pins that have wires connected to them
  • Wires & Parts – show pins that have wires connected to them and any cavity parts added such as a plug in case of a sealed connector with no wire
  • All Cavities – show all pins of all components, irrespective of connected wires and added cavities (for example if there is a 10-pin component, all the 10 pins will be shown in the table)
Javascript ID: HD_MD_ConnectionTable_Display_AD24_7

For more information, refer to the Creating a Manufacturing Drawing for a Harness Design page.

Ability to Place Comments

The ability to add comments to a Wiring Diagram (*.WirDoc) and Layout Drawing (*.LdrDoc) has been added. Comments, which are notes a user adds, can be applied to a point, object, or area on a document and may be replied to by other users. Placement can be done using the Place menu, the right-click context menu, the  icon at the top right of the design space, or the Ctrl+Alt+C shortcut keys. A placed comment in a Layout Drawing is shown in the image below.

This feature is controlled by the Harness.Comments advanced option in the Advanced Settings dialog and is enabled by default. 

For more information, refer to the Document Commenting page.

Data Management Improvement

Renamed 'Clone' Menu Command

The Clone command has been renamed Make a copy throughout the UI to clarify its function. The images below are examples of a few locations.

    

Import/Export Improvement

Options to Define Parameter Mapping for xDX Designer Imports

The Mentor xDX Designer Import Wizard now includes options that allow you to define substitution parameters for component mapping for Footprint, Designator, Comment, and Description. You can list multiple parameters in the text box by using ";" as a separator, as shown in the image below. If the first parameter does not exist, the next will be used in sequence.

For more information, refer to the Importing a Design from xDX Designer page.

Feature Made Fully Public in Altium Designer 24.7

The following feature is now officially Public with this release:

Altium Designer 24.6

Released: 18 June 2024 – Version 24.6.1 (build 21) 

Release Notes for Altium Designer 

Altium Designer 24.5

Released: 22 May 2024 – Version 24.5.2 (build 23) HotFix 1

Release Notes for Altium Designer 24.5.2

Altium Designer 24.4

Released: 16 April 2024 – Version 24.4.1 (build 13)

Release Notes for Altium Designer 24.4.1

Altium Designer 24.3

Released: 19 March 2024 – Version 24.3.1 (build 35)

Release Notes for Altium Designer 24.3.1

Altium Designer 24.2

Released: 15 February 2024 – Version 24.2.2 (build 26)

Release Notes for Altium Designer 24.2.2

Altium Designer 24.1

Released: 16 January 2024 – Version 24.1.2 (build 44)

Release Notes for Altium Designer 24.1.2 

Altium Designer 24.0

Released: 13 December 2023 – Version 24.0.1 (build 36) 

Release Notes for Altium Designer 24.0.1

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