This page details the improvements included in the initial release of Altium Designer 24, as well as those added in subsequent updates. Along with delivering a range of improvements that develop and mature the existing technologies, each update also incorporates a large number of fixes and enhancements across the software based on feedback raised by customers through the AltiumLive Community's BugCrunch system, helping you continue to create cutting-edge electronics technology.
You can choose to continue with your current version, update your current version, or install Altium Designer 24 alongside your current version to access the latest features. Your current version can be updated from within the software in the Extensions and Updates view . If you prefer to install Altium Designer 24 alongside your current version, visit the Altium Downloads page to download the installer, then choose New Installation on the Installation Mode page of the installer.
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Altium Designer 24.10
Released: 10 October 2024 – Version 24.10.1 (build 45)
Release Notes for Altium Designer
Schematic Capture Improvement
Support for Empty Sub-parts in Normal Mode
Improved single/multi-part symbol handling, extending the same features and functionality available for Alternate display modes, to the Normal display mode. For example, a component can now be represented by a single symbol in the Normal display mode and by two symbols in its Alternate mode, as shown in the image below.
If a multi-part component only has primitives defined in one sub-part, the designator suffix is hidden when that sub-part is placed on a schematic sheet, regardless of the current display mode and which sub-parts have primitives (the first sub-part or not).
If a multi-part component has empty sub-parts in its view mode (either the Normal or an Alternate mode), these sub-parts are omitted during placement.
An Unused sub-part in component violation will not occur when running a design validation if a component has sub-parts without primitives and these sub-parts are not placed on the schematic, regardless of the display mode.
Also, it is now possible to change part or display mode to one without any primitives. A warning icon is shown next to the corresponding entries in the Properties panel when an empty sub-part or display mode is selected ( ).
For more information, refer to the Searching for & Placing Components page.
PCB Improvements
Wire Bonding (Open Beta)
In this release, support for designing hybrid boards with chip-on-board (CoB) technology using Wire Bonding has been added. This feature allows you to create a component with defined Die Pads (corresponding to pins of the schematic symbol). Once placed on a schematic and synchronized (through ECO) to the PCB, it can be wired to regular pads (or any copper) on the main board using Bond Wires . When connecting to a regular pad, that pad takes on the likeness of a Bond Finger pad.
You can define a complete, simple package with defined die pads, bond finger pads, and bond wires, all as part of the component footprint.
Support for adding die pads is provided courtesy of a predefined Die component layer pair (Top Die / Bottom Die ). Note that when a die pad is placed on an extruded 3D body (also on the Top Die / Bottom Die layer), it will be automatically placed at the Overall Height of this 3D body.
For placement of bond wires (from die pad to bond finger pad, die pad to die pad, etc.), a predefined Wire Bonding component layer pair is provided (Top Wire Bonding / Bottom Wire Bonding ). Use the Place » Bond Wire command or on the Active Bar to place a bond wire. Use the fields in the Profile region of the Properties panel to specify the desired values of the Loop Height and Diameter of a bond wire, as well as the Die Bond Type (Ball or Wedge ) – .
Regular pads to which bond wires are connected (bond finger pads) can be aligned with bond wires. To do this, select bond wires and bond finger pads connected to them, right-click the selection, and then choose the Pad Actions » Align Bond Finger with Bond Wire command from the right-click menu.
An example of a footprint (in 2D and 3D views) that features wire bonding.
When using the Chip-on-Board approach, you can also place bond wires manually to connect the die pads of the chip to any copper on the main board. A bond wire will inherit the net of its source die pad. Multiple bond wires can emanate from the same die pad, and conversely, multiple bond wires can finish on the same copper on the main board.
An example of a PCB that features wire bonding.
A new Wire Bonding design rule has been added in the Routing category to support wire bonding and can be defined in the All Rules view of the Constraint Manager when accessed from a PCB and the PCB Rules and Constraints Editor dialog (when using the older approach to design rule definition and management). The rule enables constraints to be defined for the permissible distance between adjacent bond wires (Wire To Wire ), Min and Max Wire Length , and Bond Finger Margin , which is the distance/padding between a bond wire and the edge of the bond finger pad to which it is wired. The Wire Bonding design rule is supported by the batch DRC. Electrical rule checks (Un-Routed Net and Short Circuit) also apply to Wire Bonding.
In terms of manufacturing documentation, Draftsman supports wire bonding in both its regular board assembly view (for the main Chip-on-Board approach) and also the component view (for where the wire bonding ‘package’ has been fully defined within the footprint). Wire bonding information is also supported when generating regular PCB prints .
A wire bonding table report that provides information in relation to die pads and bond finger pads can be generated (in the CSV format). Use the Wire Bonding Table Report output from the Assembly Outputs region of an outjob file to add a new output of this type, or select the File » Assembly Outputs » Wire Bonding Table Report command from the main menus of the PCB editor to generate the report.
For more information, refer to the Wire Bonding page.
Phase Matching for Differential Pairs (Open Beta)
This release includes the ability to enable phase matching between the sides of a differential pair, as part of automatic diff pair length tuning.
To perform phase matching between the sides of required differential pair(s) according to the applicable Matched Lengths constraint with the Within Differential Pair Length option selected, select primitives of these diff pairs and choose the Route » Automatic Length Tuning command from the main menus. In the Auto Tuning Process dialog that opens, open a new Sawtooth tab and configure parameters of the sawtooth-based pattern as required. After clicking OK in the dialog, the sawtooth tuning patterns will be added to the sides of the differential pairs to equalize their lengths.
This feature is in Open Beta and available when the PCB.TraceTuning.PhaseTuning
option is enabled in the Advanced Settings dialog .
For more information, refer to the Length Tuning page.
Dynamic Phase Matching for Differential Pairs (Open Beta)
This release brings dynamic phase matching support for differential pairs, which is an essential consideration for high-speed PCB designs. For maximum efficiency of differential signal transmission, differential pairs need to be both statically (equalizing the length of the two sides in a pair) and dynamically (matching the phase along the entire length of the pair) phase-matched. New dynamic phase matching constraints and automatic tuning with phase compensation have been implemented, to avoid time-consuming phase mismatch detection and elimination.
The Matched Length design rule has been extended with the ability to specify dynamic phase matching constraints. When the Within Differential Pair Length option is selected, a new Dynamic Phase Matching checkbox is available. When it is enabled, you can define the following constraints:
Dynamic Phase Tolerance / Dynamic Phase Delay Tolerance – the permissible phase mismatch between the tracks in a pair above which compensation is required.
Matching Distance – the distance after exceeding the tolerance, for which compensation must be applied.
Depending on if Length Units or Delay Units are selected in the rule, the above constraints are defined in millimeters or picoseconds, respectively.
Support for this enhanced rule is available in both the All Rules view of the Constraint Manager (accessed from PCB) and the PCB Rules and Constraints Editor dialog (when using the older approach to design rule definition and management ).
Dynamic phase matching constraints configured in the Constraint Manager
Dynamic phase matching constraints configured in the PCB Rules and Constraints Editor dialog
Detected rule violations will be marked with a hatched pattern on corresponding traces in the design space (with the hatching starting at the detected point of phase mismatch, i.e., defined tolerance exceeded).
You can use the Automatic Length Tuning tool to eliminate violations of dynamic phase matching. Select the required diff pairs (any tracks of the diff pairs) and choose the Route » Automatic Length Tuning command from the main menus. On the Sawtooth tab of the Auto Tuning Process dialog that opens, set phase matching parameters as required and click OK to add sawtooth patterns required to provide dynamic phase matching of the diff pairs. Note that the electrical types of pads at either end of a routed diff pair are taken into account, so that if a source/load has been specified, tuning will be applied moving along the diff pair in the appropriate direction.
This feature is in Open Beta and available when the PCB.Rules.DiffpairPhaseMatching
option is enabled in the Advanced Settings dialog .
For more information, refer to the High Speed Rule Types page.
Routing Topology DRC Support (Open Beta)
Implementation of custom topologies defined using From-Tos can now be checked as part of the Batch DRC process. Enable the Batch option for the Routing Topology design rule type in the Design Rule Checker dialog (Tools » Design Rule Check ) to detect violations.
A violation is detected if there is an electrical connection between the pads of a From-To, and the shortest path contains at least one other pad of this net.
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Two From-Tos are created between three pads – from pad 1 to pad 2 and from pad 2 to pad 3
Routing is created according to the configuration of From-Tos – there is routing between pads 1 and 2 and between pads 2 and 3. No violation of the Routing Topology rule is detected.
Routing is created in a T-branch manner. There are no additional pads in paths according to the From-To configuration, so no violation of the Routing Topology rule is detected.
Routing is created between pad 1 and pad 3 and from pad 2 and pad 3. This routing does not match the From-To configuration because there is an additional pad 3 at the path between pad 1 and pad 2, so a violation of the Routing Topology rule for the From-To between pads 1 and 2 is detected.
Violations will not be detected for nets with a large number of pads (more than 20) or primitives (more than 1024).
This feature is in Open Beta and available when the PCB.Rules.CheckRoutingTopology
option is enabled in the Advanced Settings dialog .
For more information, refer to the Understanding Connectivity on Your PCB page.
PCB CoDesign Improvements
Display of Primitive Names in Conflicts
When a conflict between primitives of a group object is detected, names of these primitives are now included in the list of conflicts in the PCB CoDesign panel. In the image shown below, names of primitives within a group object in conflict (pads of a component) are shown before the properties of the primitives.
For more information, refer to the PCB CoDesign page.
Merging Object Properties
When the same object properties are changed from both sides and there are no conflicts in property values, these changes no longer create a conflict and can be merged, significantly reducing the number of object conflicts.
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A PCB area and properties of component J4 in the base version of the PCB document are shown here.
In the remote version of the PCB, 3D body opacity and pad numbers of J4 have been updated.
In the local working copy of the PCB, pad numbers of J4 have been updated in the same way as in the remote version.
After performing a comparison using the PCB CoDesigner panel, there is no conflict caused by changes in J4. These changes can be merged into the local copy of the PCB.
For more information, refer to the PCB CoDesign page.
Constraint Manager Improvements
Ability to Migrate to the Constraint Manager (Open Beta)
Included with this release is the ability to perform a one-time, one-way migration from using the PCB Rules and Constraints Editor dialog to using the Constraint Manager.
Use the Design » Migrate Project to Constraint Manager Flow command from the main menus in the PCB and schematic editors. The Migration Required dialog opens to warn that the migration will take place and it cannot be undone after the button is clicked. Both PCB design rules and schematic directives will be transferred into applicable corresponding constraints within the Constraint Manager. Once the migration has successfully concluded, the Constraint Manager will be opened (in the context of which editor was active when you performed the migration).
If a design rule with a default scope does not exist in the PCB Rules and Constraints Editor dialog (e.g., there is no Width rule with the scope All ), it will be created in the Constraint Manager as part of the migration process.
This feature is in Open Beta and available when the ConstraintManager.ProjectMigrationWizard
option is enabled in the Advanced Settings dialog .
For more information, refer to the Defining Design Requirements Using the Constraint Manager page.
Improvements to Directives
Add, Update, and Remove Constraints to Imported Directives
For an already-imported directive, it is now possible to add, update and remove constraints for it using the Properties panel.
To apply changes to the data in the Constraint Manager, click the button at the top-right of the Constraint Manager when it is accessed from the schematic side.
For more information, refer to the Defining Design Requirements Using the Constraint Manager page.
Warning about Discrepancy in ECO
When preparing the ECO to pass changes from the schematic to the PCB, a warning is now presented if there are directives that exist on the schematics that were not previously imported.
For more information, refer to the Defining Design Requirements Using the Constraint Manager page.
Harness Design Improvement
Auto-group Wires
For the Bulkhead Connector (the connector with the largest number of cavities), automatic grouping is applied to the wiring list in a harness manufacturing document (*.HarDwf
), ensuring that all of its cavities are correctly grouped in the From column.
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In this design, component MAIN CONTROLLER is considered the Bulkhead Connector as it has the largest number of cavities.
In the manufacturing drawing, all cavities of MAIN CONTROLLER are grouped in the From column.
View Only Mode for Harness and Multi-board Designs (Open Beta)
A view only mode has been introduced for Harness and Multi-board projects and their associated documents. This allows you to now see and explore features that were perhaps not accessible to you previously and collaborate with colleagues working on these types of projects.
When in view only mode, no updates to projects and documents are allowed/accessible. When a project has been opened in view only mode, the Projects panel will display View Only, as shown below.
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An example of view only mode for a Multi-board project. The project is labeled as View Only in the Open Project dialog and the Projects panel.
When a source document of a project is opened (as shown here for a Multi-board schematic document), it is also labeled as View Only , and the document cannot be modified.
While you cannot modify anything, you can generate outputs, such as PDFs, of source documents and defined outputs from associated OutJobs.
This feature is in Open Beta and available when the System.ViewOnlyMode.Support
option is enabled in the Advanced Settings dialog .
For more information, refer to the Designing with Multiple PCBs and Harness Design pages.
Data Management Improvements
Requirements Management (Open Beta)
For PCB design projects stored in a connected Altium 365 Workspace , this release delivers the ability to work with system requirements defined through the Requirements and Systems Portal . The latter is an advanced engineering management application used to ensure specification and performance compliance during system design development.
When enabled for your Altium 365 Workspace, the Requirements and Systems Portal integrates with your PCB design projects through the exchange of design data and formalized Requirement instances. The system requirements, as created in the Requirements and Systems Portal, can be placed as active instances on your design documents, referenced as tasks, and ultimately marked as verified to confirm requirement compliance.
In Altium Designer, the requirements are managed through the Requirements panel. Placed requirements are available in real-time to collaborating users – those that have shared access to the document – and are saved to the Workspace independently of the project without altering its constituent documents in any way.
This feature is in Open Beta and available when the EDMS.Requirements
option is enabled in the Advanced Settings dialog .
For more information, refer to the Working with Requirements page.
Ability to Change Project Parameters from a Local Template
When creating a new project using the Create Project dialog (File » New » Project ), you can now change (names and/or values) or remove parameters sourced from the selected local project template.
For more information, refer to the Creating Projects and Documents page.
SI Analyzer by Keysight (Open Beta)
More and more modern electronic devices incorporate high-speed PCB designs, and signal speeds grow as the technologies evolve (17 GHz in DDR6, 400 Gbps in QSFP++, etc.). Ensuring signal integrity (SI) is a crucial step in the high-speed design. Failure to meet the requirements of the interface developer is very likely to cause problems in further design stages, manufacturing, and performance.
To provide PCB designers with a tool for signal integrity analysis, a new solution is now available – SI Analyzer by Keysight . Provided as a software extension and available right in the Altium Designer environment, the SI Analyzer by Keysight allows performing a range of SI post-layout checks to cover the most important high-speed design parameters:
Impedance
Delay
Insertion Losses (IL)
Return Losses (RL)
This feature is in Open Beta and available when the SI Analyzer by Keysight extension is installed. Creating a new analysis document, adding/configuring nets for an analysis, as well as the review of existing SI analysis results and generation of an SI analysis report, can all be performed by anyone with a valid Altium Designer license. Performing a new SI analysis requires a valid Signal Analyzer by Keysight license. If no Signal Analyzer by Keysight license is available when running a new SI analisys, you can request a 14-day free trial using the dialog that opens.
For more information, refer to the SI Analyzer by Keysight page.
Features Made Fully Public in Altium Designer 24.10
The following features are now officially Public with this release:
Altium Designer 24.9
Released: 11 September 2024 – Version 24.9.1 (build 31)
Release Notes for Altium Designer
Key Highlights
Schematic Capture Improvement
Empty Sub-parts Omitted during Placement
If a multi-part component has empty sub-parts in its alternate view mode, these sub-parts are now omitted during placement.
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An example of a schematic symbol of a dual op amp component. The normal mode represents the component in two sub-parts. An alternate mode represents the component as a single sub-part.
When placing the component in its alternate view mode, the empty sub-part B is not placed.
For more information, refer to the Searching for & Placing Components page.
PCB Design Improvement
Ability to Overlap Courtyard Outlines
It is now possible to place components close enough that their courtyard outlines exactly overlap. When the Check clearance by component boundary option is enabled, and the Minimum Horizontal Clearance value is set to 0
in the corresponding Component Clearance design rule, there will not be any violations of this rule when component courtyard outlines exactly overlap, as shown below.
When the selection bounding box of a component is defined by the courtyard layer tracks, the centerline of these tracks is used to define the bounding box (as selecting the component shows – ). Note that this is only the case when the shape defined on the courtyard layer is a closed shape, with the track end vertices being coincident (exactly touching). Otherwise, the bounding box is defined by the smallest rectangle that encloses all of the objects on the courtyard layer, and placing components so their courtyard outlines exactly overlap will result in a violation of the Component Clearance design rule.
For more information, refer to the Placement Rule Types page.
Constraint Manager Improvements
Ability to Apply Default Keepout Rule
The Apply zero Keepout clearance option has been added to the Clearances Settings region in the Clearance options and Physical options Properties panels. When this option is enabled, a default clearance rule is applied, with a gap of ‘0’, between a keep out and all other primitives in the design. Note that this rule is not visible on any of the Constraint Manager views and, therefore, cannot be modified. If disabled, the regular clearance matrix values will be followed.
For more information, refer to the Defining Design Requirements Using the Constraint Manager page.
Ability to Enable/Disable Basic Rules
You can now enable/disable basic rules defined in the Constraint Manager's All Rules view when accessed from the PCB. Double-click a cell in the Enabled column and toggle the state of a specific basic rule between True (enabled) and False (disabled). Cells corresponding to disabled basic rules are labeled (Disabled)
and grayed out in the Physical and Electrical views.
For more information, refer to the Defining Design Requirements Using the Constraint Manager page.
Enhanced Representation of the Clearance Matrix in the All Rules View and ECO Dialog
Presentation of the Clearances Matrix on the All Rules view (when accessed from the PCB) has been improved, with all custom values now displayed as separate lines.
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In the Clearance Matrix, there are specific rules between each net class and all nets.
On the All Rules view, these rules are displayed as separate lines.
In addition, the entries and level of detail presented in the Engineering Change Order dialog when passing changes made to the Clearances Matrix have also been improved. All rules included in the matrix are now listed, including information about the scope and affected layers, as well as changes in scopes (added/removed).
For more information, refer to the Defining Design Requirements Using the Constraint Manager page.
Configuring Constraint Sets for Different Layer Stacks
When accessing the Constraint Manager from the schematic and configuring constraints for different layer stacks (e.g., for different boards in the same project), constraint sets now remember which layer stack they were created in. For the currently chosen layer stack, it is no longer possible to assign or modify a constraint set that was created for a different layer stack. The message This Constraint Set was created for a different layer stack will appear in the Properties panel when this is the case.
In addition, a caution is provided when opening a project that has constraint sets saved for custom layer stacks in an older version of the software.
For more information, refer to the Defining Design Requirements Using the Constraint Manager page.
3D-MID Design Improvements
Added Net Color Override Feature
You can now override the color of specific nets in a 3D-MID document (*.PcbDoc3D
). Use checkboxes for nets in the Nets mode of the PCB panel to enable and disable the Net Color Override feature for these nets.
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A 3D-MID document with the Net Color Override feature enabled for all nets.
A 3D-MID document with the Net Color Override feature disabled for all nets.
For more information, refer to the 3D-MID Design page.
Added Ability to Edit Tracks
Added the ability to edit a track by clicking and dragging.
Click and drag a track to add a new vertex.
Click and drag a vertex to move it.
For more information, refer to the 3D-MID Design page.
Harness Design Improvements
Project Releaser for Harness Designs (Open Beta)
This release introduces high-integrity harness design release management using the Project Releaser , a process long-enjoyed by those preparing their PCB design projects for manufacture.
The harness design release process is automated and repeatable. One-touch releasing enables you to release your design projects without the risks associated with manual release procedures. From taking a snapshot of the design files through validation and output generation, there is no interaction. If a part of the process fails, the release fails. You also get to review all generated data before finalizing the release.
The user interface to the Project Releaser is provided courtesy of a dedicated Release view. Access this view using the Project Releaser command, available from the main Project menu (with a source document for the project open as the active document) and the right-click context menu for the harness project's entry in the Projects panel.
Currently, releasing to a connected Altium 365 Workspace and local releases (offline) are supported.
This feature is in Open Beta and available when the HarnessDesign.ProjectReleaser option is enabled in the Advanced Settings dialog .
For more information, refer to the Design Project Release page.
Data Management Improvements
Ability to Change Project Parameters from a Workspace Template
When creating a new project using the Create Project dialog (File » New » Project ), you can now change (names and/or values) or remove parameters sourced from the selected Workspace project template.
For more information, refer to the Creating Projects and Documents page.
Ability to Copy Workspace-side Project-level Parameters
From the Parameters tab of the Project Options dialog (Project » Project Options ), you can now copy Workspace-side project parameters (those that appear with the icon in the dialog). Right-click the parameter entry and select the Copy command from the context menu to copy the name and value of the parameter.
For more information, refer to the Accessing, Defining & Managing Project Options page.
Ability to Share Read-only Project Snapshots
This release brings back the ability to share a read-only snapshot of a Workspace project using the Share dialog, which has been hidden since Altium Designer 24.4 .
For more information, refer to the Sharing a Design page.
Updated Message for Subscriptions of Perpetual Licenses
Text throughout the License Management UI has been updated to make it clear that subscription renewals are no longer available for perpetual licenses. After expiration, a perpetual license can still be used, but you will not have access to later updates for Altium Designer beyond that point (no new features/functionality), nor will you have access to cloud capabilities delivered through and by the Altium 365 platform.
For more information, refer to the License Management page.
Feature Made Fully Public in Altium Designer 24.9
The following feature is now officially Public with this release:
Altium Designer 24.8
Released: 21 August 2024 – Version 24.8.2 (build 39)
Release Notes for Altium Designer
Key Highlights
PCB Design Improvements
Single Layer PCB Support (Open Beta)
This release adds the ability to create a single-layer PCB, with corresponding support in the Layer Stack Manager, PCB and Draftsman documents, and generated outputs.
With this support, you can now delete either the top or bottom layer from a 2-layer stack in the Layer Stack Manager.
In a 2-layer PCB, you can now delete either the Top or Bottom Layer from its layer stack.
A single-layer stack can be created for a PCB but not a footprint.
When the layer stack has a single copper layer, the Via Types tab and the Back Drills feature will not be available in the Layer Stack Manager. Also, you can only create impedance profiles of Single-Coplanar and Differential-Coplanar types on the Impedance tab of the Layer Stack Manager for a single-layer PCB.
The Tools » Presets menu now includes a preset for a single-layer stack – show image .
If a PCB has a single signal layer, it will be reflected in the PCB editor user interface (layer tabs, the board's Properties panel, and the View Configuration panel) and in the PCB's layer stack table and drill table.
The removed layer is referenced as a side where applicable. For example, if the bottom layer is removed, it is called Bottom Side
in the Drill Layer Pair column of a drill table, as shown in the image below.
A single-layer PCB is supported in a Draftsman document and in the following outputs: Gerber, Gerber X2, ODB++, IPC-2581, Pick and Place, NC Drill, Layer Stack Report, and PCB prints.
When there are unplated thru-hole pads in a single-layer PCB, they will not be flagged in the Unplated multi-layer pad(s) detected section of the DRC report .
This feature is in Open Beta and available when the PCB.SingleLayerStack.Support
option is enabled in the Advanced Settings dialog .
For more information, refer to the Defining the Layer Stack page.
Predefined Donut Pad Shapes (Open Beta)
A predefined round Donut shape has been added to the listing of pad shapes available when defining the padstack. Use the Shape drop-down in the Properties panel to apply the Donut shape to a pad. The round Donut shape is represented as a full circle arc and is supported in the PCB List panel, Find Similar Objects dialog, and when using expressions. They are also supported on Paste/Solder Mask layers, and also when defining thermal relief connection points to a polygon pour.
The outer diameter of the round Donut pad shape is represented by D and the width is represented by W in the Properties panel, as shown in the above image highlighted in purple. Click in the respective cell to change the values.
Round Donut pad shapes are supported in ODB++, Gerber, Gerber X2, PCB prints, IPC-2581, and DXF/DWG outputs, and in PCB CoDesigner when comparing PCB documents. Also, round Donut pads are supported when importing an Xpedition design/library.
When defining a pad template, automated naming is applied in accordance with the IPC-7351 standard.
When opening a PCB using Donut-shaped pads in a previous version of the software, the information will be lost. In fact, the Donut shape will simply be converted into a series of arcs.
This feature is in Open Beta and available when the PCB.Pad.CustomShape.Donut
option is enabled in the Advanced Settings dialog .
For more information, refer to the Working with Pads & Vias page.
Routing Neck-down Rule (Open Beta)
This release implements a new routing neck-down design rule to assist you with routing in dense areas of a board.
With modern component technology, it is not uncommon for a net to be routed at different widths as the routing travels across the board. For example, routing into or out of a BGA will often require escape routes narrower than the preferred width routes allowed by the applied impedance profile. The new rule lets you define the maximum allowed total length of such narrower traces so that the route still delivers the required impedance.
The Routing Neck-Down rule can be defined in both the Physical view of the Constraint Manager and the PCB Rules and Constraints Editor dialog. Use the Neck-Down Length field to define the maximum allowed length of continuous routes (in each net scoped by the rule) whose width is between the Min Width and Preferred Width defined by the applicable Routing Width rule.
Min Width ≤ Actual Neck-down Width < Preferred Width
Alternatively, use the grid to define the allowed length per layer basis.
Enable the Routing Neck-Down rule type check for online and/or batch checking in the Design Rule Checker dialog to detect violations of the Routing Neck-Down rules in corresponding DRC modes. Detected rule violations will be marked with a hatched pattern on corresponding traces in the design space.
This feature is in Open Beta and available when the PCB.Rules.RoutingNeckdown
option is enabled in the Advanced Settings dialog .
For more information, refer to the Routing Rule Types page.
Routing Auto-shrinking (Open Beta)
In cases when a trace being routed using the interactive router cannot be routed between obstacles with the currently chosen routing width, this new feature allows to automatically shrink the width to a value that would allow routing of the trace in this location (provided that this shrunk trace would not violate the minimum allowed width from the corresponding constraint). Enable the Auto Shrinking option on the PCB Editor – Interactive Routing page of the Preferences dialog and the Properties panel during interactive routing to enable the feature.
This feature is in Open Beta and available when the PCB.Routing.EnableAutoShrinking
option is enabled in the Advanced Settings dialog .
For more information, refer to the Interactive Routing page.
Trace Centering (Open Beta)
A common desire of many designers is to center the routes when they pass between pads or vias whenever possible. The current behavior of the routing engine is to place track segments at the minimum allowed clearance defined in the design rules, leaving the task of spreading or centering the routes between the pads.
The new centering feature helps with the centering process by adding an additional clearance between the net being routed or dragged and existing pads/vias. The routing engine understands that this additional clearance is desired rather than required, so it can take some or all of it back if needed, for example, when pushing a second or third route between the existing pads/vias. If the routing engine is required to take back some of the clearance, it will take it from both sides of the routing so that it remains centered where possible.
The trace centering behavior can be configured using the new options available on the PCB Editor – Interactive Routing page of the Preferences dialog and the Properties panel during interactive routing , interactive differential pair routing or interactive sliding .
Apply Trace Centering – enables the trace centering functionality. When enabled, the following options are available to configure the functionality:
Adjust Vias – when the option is enabled, vias will be pushed to maintain the additional clearance where possible.
To prevent vias from being pushed by trace centering, you can either:
disable the Adjust Vias option. In this case, centering will not be applied between unlocked vias or
disable the Allow Via Pushing option. In this case, vias will not be pushed (even to ensure the minimum clearance from the Clearance constraint).
Added Clearance Ratio – a multiplier of the applicable clearance, which is then added to the clearance. For example, if the applicable clearance is 0.15mm
, setting the option to 2 would instruct the routing engine to clear existing pads and vias by 0.15 + 2*0.15 = 0.45mm
whenever possible. The routing engine can then reduce this clearance down to the specified clearance if required.
Disable Trace Centering When Dragging – when the option is enabled, trace centering is not applied during interactive sliding (even if the Apply Trace Centering option is enabled).
The trace centering options in the Preferences dialog
The trace centering options in the Properties panel
Additional clearance can be added around pads and vias to center the routes.
This feature is available in all routing modes, including Any Angle.
This feature is in Open Beta and available when the PCB.EnableTraceCentering
option is enabled in the Advanced Settings dialog .
For more information, refer to the Interactive Routing page.
True Zero Mitering (Open Beta)
During interactive routing, interactive differential pair routing or interactive sliding, a miter is now not created if the Miter Ratio value is set to 0
(in the corresponding Properties panel or in the PCB Editor – Interactive Routing page of the Preferences dialog), which allows you to create acute corners. In previous versions, a short miter fully covered by adjacent traces was created when Miter Ratio = 0
.
An example of a zero-miter joint between tracks during interactive routing.
This feature is in Open Beta and available when the PCB.ZeroMitersRemoving
option is enabled in the Advanced Settings dialog .
For more information, refer to the Interactive Routing page.
Constraint Manager Improvements
Modifying Directives Imported from Read-only Documents
Directives that have been imported from read-only documents (for example, device sheets and managed sheets) cannot be modified if the Make Device Sheets In Projects Read-Only option is enabled (checked) on the Data Management - Device Sheets page of the Preferences dialog. When the option is disabled (unchecked), the directives can be modified.
After directives have been imported (with the option enabled), the rule is highlighted in blue in the Constraint Manager.
For more information, refer to the Defining Design Requirements Using the Constraint Manager page.
Ability to Enable/Disable Advanced Rules
You can now enable/disable advanced rules that are defined in the All Rules view when the Constraint Manager is accessed from a PCB.
A new Enabled column is now included in the view. The column reflects the state of each advanced rule: True (enabled) or False (disabled). Double-click a cell in the column and toggle the state of a specific advanced rule. Alternatively, toggle the enabled state of advanced rules of a particular type, category, or all advanced rules using commands available from the right-click context menu for the corresponding entry in the Rule Class tree.
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The Enabled column reflects the state of each advanced rule.
Double-click a cell in the Enabled column to toggle the state of a specific advanced rule.
Right-click a rule type entry in the Rule Class tree to enable/disable advanced rules of this type.
Right-click a rule category entry in the Rule Class tree to enable/disable advanced rules in this category.
Right-click the Rule Class heading to enable/disable all advanced rules.
For more information, refer to the Defining Design Requirements Using the Constraint Manager page.
When accessing the Constraint Manager from the schematic, it is now possible to configure the Width and Differential Pairs Routing constraints for layers in a chosen layer stack.
Using a new drop-down at the top of the Constraint Manager, select an entry for a specific PCB document of the design project. If the selected PCB contains multiple layer stacks, you can choose the required stack for which constraints need to be configured using tabs in the lower part of the Constraint Manager when the corresponding rule is selected. Also, you can use a chosen Impedance Profile (where defined as part of the selected PCB’s layer stack).
For more information, refer to the Defining Design Requirements Using the Constraint Manager page.
Import/Export Constraints between Designs
Added the ability to export and import constraints between designs. To access this new feature, right-click in the Clearances , Physical , or Electrical view of the Constraint Manager, then select Export » Export Constraints for selected lines or Import » Import Constraints .
Exporting Constraints
After selecting one or more cells in the Clearances view or one or more lines in the Physical or Electrical view and then choosing Export » Export Constraints for selected lines , the Constraints for Export dialog opens with constraints for all objects that have been selected prior to choosing the command listed in the grid. Select the constraints you want to export using checkboxes (constraints related to the current view will be selected in the dialog by default). After clicking OK , the selected constraints will be exported into a file with the extension *.CstrDot
. The file can then be imported into another design.
Importing Constraints
After selecting Import » Import Constraints , the standard File Explorer dialog opens in which you can select a *.CstrDot
file to import. In the Constraints for Import dialog that opens, select the constraints you want to import from the file, then click OK . The selected constraints will be applied to corresponding objects in the target design.
If a net selected for import does not exist in the target design, an entry for it will be added to the Constraint Manager. Since there is no such net in the design, the entry will be marked with the icon. Constraint values can be copied from this entry and pasted into an existing object. The issue can be resolved by adding a net with the same net to the design and then refreshing the data in the Constraint Manager. Alternatively, an unmatched object can be removed from the Constraint Manager by right-clicking its entry and selecting Delete unmatched object – show image .
If a diff pair or xNet selected for import does not exist in the target design, it will not be added to the design.
If a net / diff pair / xNet class selected for import does not exist in the target design, it will be added to the design automatically.
For more information, refer to the Defining Design Requirements Using the Constraint Manager page.
3D-MID Design Improvements
Ability to Drag Multiple Components
In a 3D-MID document, you can now drag more than one component. Select multiple components (using the Shift+Click shortcut or other selection methods), then use Click, Hold&Drag on the selection to move all selected components at once.
For more information, refer to the 3D-MID Design page.
Displaying the 3D Substrate File Name
The name of (and full path to) the 3D substrate file is now presented in the Properties panel. When no object is selected in the 3D-MID document, open the panel's Parameters tab and locate the Pcb 3d Substrate File Name parameter.
The Pcb 3d Substrate File Name parameter value will be updated if you change the 3D substrate using the File » Change Substrate command from the main menus. Note that it will not be updated if the 3D substrate file is renamed (e.g., through the Windows File Explorer ).
For more information, refer to the 3D-MID Design page.
Harness Design Improvements
The ability to add comments to a Draftsman document (*.HarDwf
) has been added. Comments, which are notes a user adds, can be applied to a point, object, or area and can be replied to by other users. Placement can be done using the Place menu, the right-click context menu, the icon at the top right of the design space, or the Ctrl+Alt+C shortcut keys. A comment placed in a Draftsman document is shown in the image below.
For more information, refer to the Document Commenting page.
Layout Label Text Display in BOM
This release adds the ability to display the text value for a layout label in the BOM. Enable the Label Text column in the ActiveBOM document or the BOM table placed in a Draftsman document to display the layout label text. Note that a layout label is shown in the BOM when its Type is set to Standard
.
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The Type property of layout labels on the Layout Drawing is set to Standard
.
In the ActiveBOM document, use the Properties panel to enable visibility of the Label Text column for the BOM.
In the Draftsman document, use the Properties panel to enable visibility of the Label Text column for the BOM table when it is selected.
For more information, refer to the Creating the Layout Drawing page.
Support for Strip Length and Pull Off Length for Crimp-type Cavities
You can now specify the Strip Length and Pull Off Length when defining a crimp-type cavity in the Wiring Diagram (*.WirDoc
).
Both properties are included in the wiring list and connection table objects in a Draftsman document (*.HarDwf
) with column headings as follows:
For a wiring list:
FromCrimpStripLength
FromCrimpPullOffLength
ToCrimpStripLength
ToCrimpPullOffLength
For a connection table:
CrimpPullOffLength
CrimpStripLength
For more information, refer to the Defining the Wiring Diagram page.
Switching to .NET 6
With this release, Altium Designer switches from using .NET Framework 4.8 to .NET 6. The main reason for the switch is that Microsoft considers the .NET Framework obsolete. Although Microsoft will continue to support it for many years, it will not add any new functionality or features. All new developments and features happen in the .NET Core family that .NET 6 is part of. As a result, the switch is necessary at some point.
Additionally, .NET 6 is much faster than .NET Framework. In our tests, schematic and Draftsman showed great improvements. Many other areas, such as BOM, compilation, and library creation, show smaller improvements.
Lastly, we do not need to install any .NET Framework; we can bundle .NET 6 with Altium Designer. This will remove the issues caused by installing the .NET Framework and when Windows updates interfered.
Any Third Party extensions that were found to be incompatible with .NET 6 have been removed from the software, starting at this release. If later, updated versions of these extensions are made to be compatible with Altium Designer 24.8 (or beyond), contact beta.program@altium.com to get them added back to the installation.
For more information, refer to the System Requirements page.
Data Management Improvements
New 'Number of Pads Exceeds Number of Pins' Check for Components
Added the new Number of Pads exceeds Number of Pins violation type as part of the validation checks that can be configured for a Workspace component. A violation of this type occurs when the number of pads (SMD pads placed on copper layers and plated thru-hole pads) in a footprint model assigned to a component being validated exceeds the number of pins in the component's schematic symbol model.
In this example, two violations appear for a component – one for each footprint where the number of pads exceeds the number of schematic symbol pins.
The default mode of the Number of Pads exceeds Number of Pins violation is Error . If required, it can be configured on the Data Management – Component Rule Checks page of the Preferences dialog.
For more information, refer to the Validating a Component page.
Support for Item ID Matching to an External DB Parameter
A database parameter can now be mapped to a Workspace component's Item ID for a database component synchronization process. Use the Parameter Mapping region of the Properties panel when the required table is selected in the CmpSync document to map the ID parameter to a source database parameter.
For more information, refer to the Component Database to Workspace Data Synchronization page.
Feature Made Fully Public in Altium Designer 24.8
The following feature is now officially Public with this release:
Altium Designer 24.7
Released: 23 July 2024 – Version 24.7.2 (build 38)
Release Notes for Altium Designer
Key Highlights
Schematic Capture Improvements
Enhancement to Multi-part Components
If a multi-part component only has primitives defined in one sub-part, the designator suffix is now hidden when that sub-part is placed on a schematic sheet. This is only for alternate display modes; the suffix is always shown for the Normal display mode. Also, it is no longer possible to select a sub-part (or alternate display mode) when that sub-part/mode has no primitives.
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An example of a schematic symbol of a dual op amp component. The normal mode represents the component in two sub-parts. An alternate mode represents the component as a single sub-part.
On the schematic sheet, the designator suffix is not shown for the sub-part when it is the only sub-part in the selected alternate mode.
It is no longer possible to select a sub-part when that sub-part has no primitives.
It is no longer possible to select a alternate display mode when that mode has no primitives.
For more information, refer to the Creating a Schematic Symbol page.
Added New Port Violation
A new violation type has been added to the Violations Associated with Nets category on the Project Options dialog's Error Reporting tab to detect a flat design port that does not have a corresponding/matching port in any source schematic documents. The Port with no matching ports error violation will occur when there is no matching port, or a port is not connected. The default status of the violation is No Report
.
This violation type will only be detected if the Net Identifier Scope option on the Options tab of the Project Options dialog is set to either Flat (Only ports global)
or Global (Netlabels and ports global)
.
For more information, refer to the Validating Your Design Project page.
You can now choose an alternate part with no changes to a symbol on a schematic or needing to add a footprint to the PCB. In the Properties panel, enable the Do not overwrite schematic symbol and/or Do not overwrite PCB footprint options as needed, as shown in the image below. Parameters for the chosen alternate are faithfully presented in the ActiveBOM.
For more information, refer to the Working with the Variant Manager page.
PCB Design Improvements
Added Additional Options to Layer Stack Manager
Parameters have been added to the Layer Stack Manager Properties panel for a few key parameters that are important for Power Integrity simulation. Copper Resistance and Via Plating Thickness can be defined using the Properties panel as part of the properties for a board’s layer stack.
These parameters are included when exporting the board into Ansys EDB format . The Power Analyzer by Keysight tool also supports the Via Plating Thickness parameter. The value of this parameter is displayed in the Configuration region of the analyzer document.
For more information, refer to the Defining the Layer Stack page.
Return Path Via Check (Open Beta)
When a high-speed signal passes from one reference plane to another, there should also be return vias to pass the return signals between the planes. In order to check if such a via exists within a specific distance from a signal via, the Return Path rule has been extended with a new Max Stitch Via Distance option with which you can define if a return path via should be present within a given distance (a default value is 1.5mm
) from a via of the scoped signal. The return path via should provide connection to the reference layer defined in Layer Stack Manager for the corresponding impedance profile.
An example of the max stitch via distance constraint configured in the Constraint Manager
An example of the max stitch via distance constraint configured in the PCB Rules and Constraints Editor dialog
When the Max Stitch Via Distance option is enabled in the rule and a non-zero value is defined for it, the presence of a return path via within the specified distance is checked as part of the Batch DRC.
An example of the max stitch via distance constraint violation. Here, a via of net DQS4R_N
has no return path via at the specified distance.
This feature is in Open Beta and available when the
PCB.Rules.CheckReturnPathVia
option is enabled in the
Advanced Settings dialog .
For more information, refer to the High Speed Design page.
Enhanced Trace Loop Removal (Open Beta)
Introduced a new implementation of automatic loop removal in the Interactive Router. This update improves behavior when using the loop removal functionality when routing using the Any Angle corner style, improves behavior of via removal after loop removal (see below), and lays the foundation for future enhancements.
Remove Via After Loop Removal
When there is a direct via-to-pad connection, the via will now be removed if deemed no longer needed after loop removal (provided the Remove Loops With Vias option is enabled in the Properties panel for interactive routing).
This feature is in Open Beta and available when the
Legacy.PCB.Routing.LoopRemoval
option is disabled in the
Advanced Settings dialog .
For more information, refer to the Interactive Routing and Differential Pair Routing pages.
PCB CoDesign Improvement
Added Ability to Leave Feedback to Altium
A Leave Feedback control has been added to the PCB CoDesign panel, allowing you to send feedback directly to Altium Developers with suggestions or issues related only to the PCB CoDesign feature.
For more information, refer to the PCB CoDesign page.
Constraint Manager Improvements
Import/Export of Constraint Sets between Designs
This feature allows you to import and export constraint sets, which enables you to quickly reuse constraint information between different board designs. To access this new feature, right-click in the Clearances , Physical , or Electrical view of the Constraint Manager, then select Export Constraint Sets or Import Constraint Sets .
Exporting Constraint Sets
After selecting Export Constraint Sets , the Constraint Sets for Export dialog opens with all constraint sets that are currently present in the design listed in the grid. Select the constraint sets you want to export using checkboxes, then click OK . The selected constraint sets will be exported into a file with the extension *.CstrDot
. The file can then be imported into another design.
Importing Constraint Sets
After selecting Import Constraint Sets , the standard File Explorer dialog opens in which you can select a *.CstrDot
file to import. In the Constraint Sets for Import dialog that opens, select the constraint sets you want to import from the file, then click OK . Imported constraint sets can be inspected in the Properties panel when the corresponding view of the Constraint Manager is selected and can be applied to objects.
For more information, refer to the Defining Design Requirements Using the Constraint Manager page.
A new global option allows you to specify whether clearances between pads in the same component footprint are ignored. The option is available from the Clearances and Physical views when the Constraint Manager is accessed from either the schematic or PCB. Toggle the Ignore Pad to Pad clearances within a footprint option in the Clearances Settings region of the Properties panel to apply the setting to all defined clearance rules.
For more information, refer to the Defining Design Requirements Using the Constraint Manager page.
Harness Design Improvements
Display Options for Cavities in Connection Table
You now have the ability to control the type of cavities that are displayed in a Connection Table of a Harness Manufacturing document (*.HarDwf
). Use the Display drop-down in the Properties panel to select the desired cavities to be displayed:
Wires Only – show only pins that have wires connected to them
Wires & Parts – show pins that have wires connected to them and any cavity parts added such as a plug in case of a sealed connector with no wire
All Cavities – show all pins of all components, irrespective of connected wires and added cavities (for example if there is a 10-pin component, all the 10 pins will be shown in the table)
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For more information, refer to the Creating a Manufacturing Drawing for a Harness Design page.
The ability to add comments to a Wiring Diagram (*.WirDoc
) and Layout Drawing (*.LdrDoc
) has been added. Comments, which are notes a user adds, can be applied to a point, object, or area on a document and may be replied to by other users. Placement can be done using the Place menu, the right-click context menu, the icon at the top right of the design space, or the Ctrl+Alt+C shortcut keys. A placed comment in a Layout Drawing is shown in the image below.
This feature is controlled by the
Harness.Comments
advanced option in the
Advanced Settings dialog and is enabled by default.
For more information, refer to the Document Commenting page.
Data Management Improvement
Renamed 'Clone' Menu Command
The Clone command has been renamed Make a copy throughout the UI to clarify its function. The images below are examples of a few locations.
Import/Export Improvement
Options to Define Parameter Mapping for xDX Designer Imports
The Mentor xDX Designer Import Wizard now includes options that allow you to define substitution parameters for component mapping for Footprint, Designator, Comment, and Description. You can list multiple parameters in the text box by using ";" as a separator, as shown in the image below. If the first parameter does not exist, the next will be used in sequence.
For more information, refer to the Importing a Design from xDX Designer page.
Feature Made Fully Public in Altium Designer 24.7
The following feature is now officially Public with this release:
Altium Designer 24.6
Released: 18 June 2024 – Version 24.6.1 (build 21)
Release Notes for Altium Designer
Key Highlights
PCB Design Improvement
Ability to Disable Automatic Update of Drill Symbol Data (Open Beta)
To improve performance, the automatic (live) update of drill symbols is now disabled.
To update drill symbol data in the PCB panel in its Hole Size Editor mode, right-click within a region of the panel in this mode and select the Refresh command.
To update drill symbol data in a drill table, click the Refresh button in the Actions region of the Properties panel when the drill table is selected.
The drill symbol data is updated automatically when saving the PCB document and for any outputs that contain this data.
This feature is in Open Beta and available when the
PCB.LiveDrillSymbols
option is disabled in the
Advanced Settings dialog .
3D-MID Design Improvements
Added support for the placement of components onto a substrate when footprints contain not just standard pads but also solid regions and/or fills. This enables you to place components with more complex-shaped footprints onto your substrates, including RF shapes (e.g., antennas).
Support Routing Along 'Natural' Lines
Added the ability to route along more 'natural' lines on the surface of the 3D substrate by using the new ‘UV’ Plane Kind for the alignment grid. Rather than the more rigid grids generated using the traditional XYZ planes, the UV plane generates a grid based on the surfaces of the substrate, providing more natural gridlines that follow the curves of the substrate.
When no object is selected in the design space of the 3D-MID document, select UV from the Plane Kind drop-down in the Alignment grid region of the Properties panel to select the new plane kind.
Ability to Override Snapping Priority
The ability to override snapping priority has been added, making it possible to snap to the grid rather than to that trace's centerline when routing to/from an existing trace. The snapping priority controls are accessed using the Objects for snapping button ( ) on the Active Bar .
Data Management Improvements
Added Ability to Preserve Lifecycle State when Releasing
Added ability to preserve a component's current lifecycle state when releasing into a new revision in the connected Workspace from the Component Editor (in its Single Component Editing or Batch Component Editing mode). Control is provided courtesy of a new option – Preserve lifecycle state (not recommended) – available in the Edit Revision dialog when re-releasing.
This ability is available for those with assigned Allow to skip lifecycle state change for new revisions operational permission (learn more about Setting Global Operation Permissions for a Workspace ).
Added Favorite Filters in the Manufacturer Part Search Panel
'Favorite filter' functionality has been added to the Manufacturer Part Search panel, which allows you to select certain parameter types as favorites. Once selected, they move to the top of the list in the current component category. To select a favorite, hover to the right of a parameter filter’s name, then click the star icon. Favorite filter settings apply to and are saved for individual component categories.
Support SiliconExpert Data in Non-Workspace Projects
Columns of data from SiliconExpert can now be added to the ActiveBOM document not only of a project hosted in the connected Workspace but also a non-Workspace project.
Import/Export Improvements
KiCad Importer Improvement
You can now import KiCad designs created using KiCad version 7 or 8 software into Altium Designer.
Ansys EDB Exporter Improvements
When exporting a PCB into Ansys EDB format, net classes and differential pairs are now supported and the 'Negative' attribute is now disabled for plane layers.
Rebranded SiSoft to MathWorks
In accordance with external rebranding, SiSoft has been replaced with MathWorks throughout the UI (in the File » Export main menu of the PCB editor, the Add New Export Output menu in an OutJob file, the exporter on the Configure Platform page of the Extensions and Updates view, and the Altium Designer installation wizard).
Backward compatibility of defined MathWorks outputs in an OutJob file in Altium Designer 24.6 (and later) is not supported. As such, outputs will not be visible when opening the OutJob in an older version of Altium Designer. SiSoft outputs configured in an OutJob file in a previous version of Altium Designer will, however, be transformed into MathWorks outputs when the file is opened in Altium Designer 24.6 (and later).
Altium Designer 24.5
Released: 22 May 2024 – Version 24.5.2 (build 23) HotFix 1
Release Notes for Altium Designer
Key Highlights
Schematic Capture Improvement
Automatic Addition of Supply Nets Rule (Open Beta)
When updating the PCB document, the Supply Nets design rule is now suggested to be added to each power net (i.e. a net containing a power port or that has been assigned the Power Net parameter through a parameter set ).
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A Supply Nets rule is added to a net with an attached power port object.
A Supply Nets rule is added to a net with an attached parameter set for which the Power Net option is enabled.
This feature is in Open Beta and available when the
Schematic.AutoGenerateSupplyNetsRule
option is enabled in the
Advanced Settings dialog .
PCB Design Improvement
This release adds measures to prevent inadvertent mirroring of a footprint along its X/Y axes, typically the result of using the associated keyboard shortcuts to mirror a component or the room to which it has been associated. Such mirrored footprints can, if undetected, lead to costly re-spins. To cater for early detection of such mirroring, the following have been implemented:
A new warning dialog is presented when using a keyboard shortcut to mirror a component/room that asks you to explicitly confirm that mirroring on the same side of the board is indeed what you truly mean to do. By default, the No button is highlighted, making it more of a conscious decision to click Yes to proceed with mirroring.
A new Components with Mirrored Footprints check (disabled by default) has been added to the Components region of the PCB Health Check Monitor (which is configured on the Health Check tab of the Properties panel when no object is selected in the PCB document), which detects changes in pins between a placed component footprint in the PCB design space and the corresponding footprint in the applicable source library. You can fix such an issue, which removes mirroring for the placed footprint instance so that it is the same as defined in the source library.
Note that only mirroring-related elements (pins, overlays and 3D bodies) are considered when applying the fix. Other changes to the placed component footprint, such as rotation, remain untouched.
The Update From PCB Libraries tool (Tools » Update From PCB Libraries ) has been enhanced to detect changes in designators and 3D bodies (across all layers), with differences listed on the Properties tab. Fixes to inadvertent mirroring of footprints effected through an ECO generated from the tool are exactly the same as those applied from the Health Check Monitor.
The Footprint Comparison Report that can be generated from the Update From PCB Libraries tool (or through an OutJob) has also been enhanced to support the ‘mirrored footprint detection’ – show image .
This feature is in Open Beta and available when the PCB.Component.MirroredFootprint option is enabled in the Advanced Settings dialog .
ODB++ Improvements (Open Beta)
This release sees enhancements in ODB++ output generation described below.
Ability to Switch between ODB++ Versions
This feature allows you to switch between ODB++ version 8.1 and legacy version 7.0. Use the ODB++ Version option in the ODB++ Setup dialog to select the required version.
When the feature's advanced option is disabled, ODB++ version 8.0 formatted outputs are generated.
When the v. 8.1 option is selected as the ODB++ Version in the ODB++ Setup dialog, you can select Millimeters or Inches as the Units . When the v. 7.0 option is selected, Inches are selected by default and cannot be changed.
Support for Design Variants
When generating ODB++ version 8.1 formatted outputs, information about all design variants (including 'No Variations') can be included by enabling the Include Variants Data option in the ODB++ Setup dialog.
When this option is enabled, the following information is included in the outputs:
State of each component inside any exported variant (fitted / not fitted).
Information about alternate part(s) on the component level for any exported variant.
Parameters of each component according to the variation.
Custom parameters applied to each variant/component.
When this option is disabled, the output is generated for the variant selected in the Outjob file or, when the output is generated directly from the PCB editor (File » Fabrication Outputs » ODB++ ), the currently active variant selected in the Projects panel.
When ODB++ generation is configured from an Outjob file, and the Include Variants Data option is enabled, all design variants are included in the ODB++ output, irrespective of which variant is selected for the Outjob file or for the output.
Note that variations for paste masks are not considered. If paste mask variations should be included, make sure that the Allow Variation for Paste Mask option is enabled in the settings of required variants and generate outputs for each variant individually, with the Include Variants Data option disabled in the ODB++ Setup dialog.
Support for Layer Subtypes
To provide support for rigid-flex PCB manufacturing, information about rigid and flex layer subtypes is included when generating ODB++ version 8.1 formatted outputs. The following layer subtypes are supported:
COVERLAY
– clearances of a coverlay layer.
STIFFENER
– shapes and locations where stiffener material is placed on the PCB.
BEND_AREA
– for labeling areas on the PCB bent when the PCB is in use.
FLEX_AREA
– stores the geometries of the flex portions of the board.
RIGID_AREA
– stores the geometries of the rigid portions of the board.
SIGNAL_FLEX
– signal (copper) layer on flex laminate. Used to distinguish from signal on rigid laminate in rigid-flex boards.
PG_FLEX
– power and ground (copper) layer on flex laminate. Used to distinguish from power and ground layer on rigid laminate in rigid-flex boards.
Support for Zones
When generating ODB++ version 8.1 formatted outputs for rigid-flex boards, the zones
file is now generated. The resulting zones
file (located in the \steps\pcb
folder of the generated output) contains information about all of the zones (board regions) defined in the design, including layers involved and coordinates for each zone’s outline.
Support for Geometry on the Stiffener Layer
When generating ODB++ output in v8.1 format, support has been added for generating geometry information (profile and thickness) on the stiffener layer – show image .
Updates for Backdrill Generation
In order to correctly treat backdrills, they are now stopping in the previous layer to that defined in the Layer Stack Manager in generated ODB++ version 8.1 formatted outputs.
Constraint Manager Improvements
Importing Directives Enhancements
The new Import values to Constraint Manager dialog displays a summary of the import from the schematic to the Constraint Manager that will be completed by clicking the Import button in the dialog. The dialog is accessed by right-clicking in the Constraint Manager (when accessed from a schematic document). Click the Import button to import the listed changes to the Constraint Manager.
Directives that have been imported are displayed in blue, and the symbols for a parameter set and differential pairs have been updated, as shown below.
When directives have been imported, the Properties panel now displays the rules from the Constraint Manager, as shown below.
Support for xNets on PCB Side
Added support for creating xNets and xNet classes in the Constraint Manager, when accessed from the PCB.
Defined xNets and xNet classes can be propagated between the PCB and schematic sides through the bidirectional ECO process.
Create xSignals Automatically for 2-pin Nets
xSignals are now automatically created for 2-pin nets. When the Custom topology is selected for a 2-pin net, its pins are automatically added as nodes to the topology editing area, and the proposed xSignal is automatically selected.
Harness Design Improvements
Added BOM Control for Harness Objects
A Type field has been added to various objects in the Wiring Diagram (*.WirDoc
) and Layout Drawing (*.LdrDoc
) to control inclusion in the BOM. Use the drop-down associated with the field in the Properties panel, then choose the desired option: Standard
or Standard (No BOM)
. The objects for which this control is available are listed below.
Wiring Diagram
Harness Wire
Harness Cable
Shield
Layout Drawing
Harness Covering
Layout Label
Added Support for Templates in a Workspace
Support has been added for creating, uploading, editing, and reusing Harness Wiring Diagram and Harness Layout Drawing templates in a connected Altium 365 Workspace.
Use the Data Management – Templates page of the Preferences dialog to manage your templates. Use the Harness Wiring and Harness Layout commands in the drop-down of the Add button to add a new template of the corresponding type or use the right-click menu to manage existing templates.
The Harness Wiring Template
and Harness Layout Template
content types and Harness Wiring Templates and Harness Layout Templates folder types provide for storing templates of corresponding types in the Workspace.
Single Wire Color Parameter Visibility
Secondary and tertiary color parameters that are assigned to a wire in the Wiring Diagram (*.WirDoc
) no longer have a separate visibility icon in the Properties panel. The Color parameter controls the visibility of the parameter and displays the combined value of all defined wire colors, as shown in the image below.
Added 'Include Cut' Parameter to Wires
A new Include Cut parameter has been added to the wire object. The parameter controls whether to include the wire in the Wiring List that is placed in a Harness Draftsman document (*.HarDwf
). By default, the Value for this parameter is Yes
(include); change the Value to No
to exclude. The parameter is added automatically for a newly placed wire. The parameter must be added manually for existing wires if you do not want them included in the Wiring List.
Data Management Improvements
Preventing Saving Files in Conflict States to Workspace
When attempting to use the Save to Server command when local conflicts still exist (i.e. a project contains files in the state now called Conflict Prevention , with the VCS icon in the Projects panel), the new Action Required information dialog will be presented, listing the conflicting file(s) that need resolution. Such files will now have the Conflict Detected state with the VCS icon. Use the VCS content menu of a document in the Conflict Detected state to resolve the conflict by updating the document with its latest revision from the Workspace or by using the local document.
The context menu accessed by clicking the version control status icons in the Projects panel has been updated with more focused actions that can be performed, depending on the type of document for documents in Modified , Out of date and Conflict Prevention states.
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Javascript ID: Pnl_Projects_VCSMenu_AD24_5
The VCS context menu of documents in Out of date , Conflict Prevention and Conflict Detected states includes a new Open Remote Document Version command that opens the latest document revisions from the Workspace in a new document tab.
For schematic and PCB documents in Modified , Out of date , Conflict Prevention, and Conflict Detected states, the menu also includes a command to compare the local document with the latest document revisions in the Workspace using the Workspace's schematic comparison functionality for a schematic document or the PCB CoDesign functionality for a PCB document.
For documents that have a graphical design space (schematic document, Draftsman document, etc.), a notification banner that shows the document's Out of date , Conflict Prevention or Conflict Detected VCS state and provides controls to perform appropriate actions is now presented at the bottom of the design space – show image .
When a project contains only documents in Out of date and No Modification states, an Update from Server control now appears next to the project name in the Projects panel. Click the control to retrieve the latest documents of outdated files from the Workspace – show image .
Support for Pulling Part Data from Z2Data
In this release, support for pulling advanced parametric data for parts from Z2Data has been added. If you have access to the Z2Data integration functionality, you can pull high-quality data provided by Z2Data for manufacturer parts, such as part parameters and alternatives. The Z2Data integration provides advanced comprehensive supply chain and component data, including detailed part datasheet, lifecycle data, RoHS & REACH status, and Z2Data’s proprietary 6-point part scoring algorithm.
The Z2Data integration is paid functionality that is currently in the early access stage. To become an early adopter of the functionality, contact Altium using the form on the Altium 365 Z2Data Integration page .
Note that after gaining access to the functionality, the Z2Data application must be configured on the Admin – Apps page of your Altium 365 Workspace's browser interface – learn more .
Added SiliconExpert Datasheet References
Datasheets provided by SiliconExpert can now be accessed from Altium Designer.
The Manufacturer Part Search panel lists a datasheet from SiliconExpert in the Datasheets region when the manufacturer part is selected.
The Datasheet button in part choices and solutions in ActiveBOM opens a datasheet from SiliconExpert.
Datasheets provided by SiliconExpert are presented by default. Therefore, there is no need to request SiliconExpert data for a part (and hence, use the quota from your SiliconExpert package) to access a SiliconExpert datasheet for it.
Feature Made Fully Public in Altium Designer 24.5
The following feature is now officially Public with this release:
Altium Designer 24.4
Released: 16 April 2024 – Version 24.4.1 (build 13)
Release Notes for Altium Designer
Key Highlights
Schematic Capture Improvement
Use of Multi-part Components with Alternate Modes
This release announces support for presenting a multi-part component as either a single symbol (all sub-parts) or multiple symbols (one for each individual sub-part) using only a single component through defined Normal and Alternate Modes.
An example of a schematic symbol of a dual op amp component. The normal mode represents the component in two symbols. An alternate mode represents the component as a single symbol.
Now, if a component has sub-parts without primitives, not placing these sub-parts on the schematic will no longer cause an Unused sub-part in component violation when running a design validation (provided parts with no primitives are listed below all parts that have primitives in the list of symbol parts that can be seen in the SCH Library panel).
PCB Design Improvements
Selection Box for Component 'Push' and 'Avoid'
User-defined geometries for the component selection bounding box (following the PCB.ComponentSelection
advanced setting – learn more ) are now observed when moving a component in Push or Avoid Obstacles mode.
Added 'Obey Rules' Option for Polygon Pour Properties
For a placed solid polygon pour, a new Obey Rules option is available as part of its properties, which is used when removing necks less than a certain width. Enabled by default for new polygons, it takes the value from the applicable minimum Width constraint.
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Javascript ID: PolygonPour_ObeyRules
When the Obey Rules option is disabled for a polygon pour, the minimum width of allowed necks is determined by the Remove Necks Less Than field. In this example, this value is 0.12mm
, and necks of approximately 0.14 mm are allowed.
When the Obey Rules option is enabled, the minimum width of allowed necks is determined by the minimum width value from the applicable Width constraint. In this example, this value is 0.15mm
, and necks less than this value are removed.
Constraint Manager Improvements
Added Indication of Sync Status with Directives
This release adds an indicator of sync status between a constraint in the Constraint Manager and the equivalent defined in a directive placed on a schematic.
When an object in the schematic has a parameter set or differential pair directive placed on it, and this directive has constraint values that differ from values defined for the same object in the Constraint Manager , these values will be marked with an orange bar at the left side of the corresponding cell in the Physical or Electrical view of the Constraint Manager when the Constraint Manager is accessed from a schematic (e.g., ).
When values of the constraint are in sync between the Constraint Manager and the directive, the indication changes to a green bar (e.g., ).
When the object has no existing constraints, use the Import from Directives command from the right-click menu of the view to import data from directives to the Constraint Manager . Note that if a constraint value that has been synchronized with a directive is edited in the Constraint Manager after using the Import from Directives command, it will not be synchronized after subsequently using the Import from Directives command again.
Note that after synchronizing data by importing data from directives to the Constraint Manager and saving changes in the Constraint Manager , the controls to add a new or edit/remove an existing net class, diff pair class, components class, or rule will be grayed out in the Properties panel for the corresponding directives.
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Javascript ID: CM_ImportFromDirectives_SyncIndication
Net A00
has a Parameter Set directive placed on it, and this directive has a Width constraint assigned.
In the Physical view of the Constraint Manager , cells related to width constraints of net A00
have an orange bar that indicates these values are not in sync with the directive.
After using the Import from Directives command, data from directives are imported to the Constraint Manager , and the cells now have a green bar that indicates that these values are in sync with the directive.
Note that in directive properties, controls to add, edit and remove classes and rules are now grayed out.
Propagating Width/Gap Values
From the Physical view of the Constraint Manager , a value entered in the top grid for a single net or xNet (Min Width or Preferred Width ), differential pair (Min Width , Preferred Width , or Preferred Diff Pair Gap ), or net/xNet/diff pair class will now be propagated to corresponding width (Min Width /Preferred Width /Max Width ) or gap (Min Gap /Preferred Gap /Max Gap ) fields in the constraint regions below. Note that an entered value will be propagated to other fields only if the object does not have the specific rule defined.
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Javascript ID: CM_PropagateWidth
Net A00
currently has no width constraint assigned (i.e. these constraints are inherited from the All Nets
net class).
After entering a value for the width constraint of the net (the Min Width constraint in this example)...
...the value propagates to other fields of the width constraint (Preferred Width and Max Width ).
Draftsman Improvement
Show Only Not Fitted Components in BOM Table
Support is now available for placing a BOM table into a manufacturing drawing created for a PCB design project (*.PCBDwf
), presenting only those components that are Not Fitted for the currently selected design variant . To do this, select the Not Fitted
option from the Show Components drop-down in the Properties panel for the selected BOM table.
You can also select the Replaced
option from the drop-down to show only components for which alternate parts have been selected or fitted components with varied parameter values in the current variant.
Currently, a BOM table with the Fitted
, Not Fitted
or Replaced
options selected for Show Components works with Base
and Flat
options for View Mode (not Consolidated
).
Data Management Improvements
Show Real Value for SiliconExpert YTEOL Parameter
When a part has the YTEOL parameter provided by SiliconExpert with a value greater than 5 years, the real value of this parameter is now presented in all places where summary data on the part is presented (e.g., the header of the Details pane in the Manufacturer Part Search or Components panel, or part choices) instead of the 5+ years
entry.
References to SiliconExpert Compliance Datasheets
Added support for references to SiliconExpert compliance datasheets to various places where SiliconExpert data can be used, including ActiveBOM (*.BomDoc
), Manufacturer Part Search , Components, and Explorer panels, and when generating a BOM output (in PDF or Excel format) through an Output Job.
An example of accessing a compliance datasheet from an ActiveBOM document.
An example of accessing a compliance datasheet from the Manufacturer Part Search panel.
Display Item Name for Workspace Content
For a Workspace content type that can be directly edited, the name of the item being created, cloned or edited is now shown in the Projects panel and the document tab, rather than its Item-Revision ID.
An example of editing Workspace content (schematic snippet, managed schematic sheet, component template, Draftsman sheet template, and layerstack) and displaying item names in the Projects panel and document tab.
When using Database to Workspace component synchronization (*.CmpSync
) and part supplier synchronization (*.PrtSync
), files in the latest MS Access database format (*.accdb
) can now be used as the data source.
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Javascript ID: accdb_support_AD24_4
Features Made Fully Public in Altium Designer 24.4
The following features are now officially Public with this release:
Altium Designer 24.3
Released: 19 March 2024 – Version 24.3.1 (build 35)
Release Notes for Altium Designer
Key Highlights
PCB Design Improvements
Pad Corner Radius/Chamfer as an Absolute Value (Open Beta)
In this release, the ability to define pad corner radius/chamfer as an absolute value (in mil or mm) has been added.
When a pad of the Rounded Rectangle or Chamfered Rectangle shape (on a copper, paste or solder layer) is selected in the PCB or PCB Footprint editor, enter a value to the Corner Radius field to define the radius/chamfer as an absolute value (with the default measurement units). Note that the absolute value of the pad corner radius/chamfer must be less than or equal to half of the shortest pad side. The calculated percentage value will be shown at the right of the field.
Enter a value to the Corner Radius field to define it as an absolute value.
Enter a value followed by the %
symbol to define the radius/chamfer as the percentage of half of the pad's shortest side (as in previous versions).
The absolute value of the pad corner radius chamfer is also supported by the PCB List and PCBLIB List panels , the Find Similar Objects dialog , and the Pad/Via Template editor . Also, the following query keywords can now be used in expressions:
Keyword
Summary
Pad_CornerRadius_Value_AllLayers
Pad_CornerRadius_Value_TopLayer
Pad_CornerRadius_Value_BottomLayer
Pad_CornerRadius_Value_MidLayer<n>
(where n
= 1..30)
Return pad objects whose Pad Corner Radius Size property for the corresponding layer complies with the query.
For example, the AsMM(Pad_CornerRadius_Value_TopLayer) > '0.1'
query returns pad objects whose Pad Corner Radius Size (Top Layer) property is greater than 0.1mm
.
Pad_CornerRadius_UsesPercent_AllLayers
Pad_CornerRadius_UsesPercent_TopLayer
Pad_CornerRadius_UsesPercent_BottomLayer
Pad_CornerRadius_UsesPercent_MidLayer<n>
(where n
= 1..30)
Return pad objects whose Pad Corner Radius Uses Percent property for the corresponding layer complies with the query.
For example, the Pad_CornerRadius_UsesPercent_MidLayer2 = 'False'
query returns pad objects whose Pad Corner Radius Uses Percent (Mid Layer 2) property is disabled (i.e. an absolute value is used to define the pad radius on this layer).
Note that the existing Pad_CornerRadius_AllLayers
, Pad_CornerRadius_TopLayer
, Pad_CornerRadius_BottomLayer
and Pad_CornerRadius_MidLayer<n>
(where n
= 1..30) are still used to scope pad objects whose Pad Corner Radius (%) property for the corresponding layer complies with the query.
Support for pad corner radius/chamfer defined as an absolute value has also been added to the Import Wizard when importing an Xpedition design .
This feature is in Open Beta and available when the
PCB.Pad.CustomShape.CornerRadiusAbsolute
option is enabled in the
Advanced Settings dialog .
PCB Replication Improvements
Enhanced Error Notifications
If a missing pin connection in the selected Source Block is detected when running the Layout Replication tool, the warning dialog will notify you about the missing connection.
Click the link in the dialog to cross-probe to the offending object.
Added 'Busy' State for PCB Replication
To provide a more responsive UI for the PCB replication process, the indicators of the feature 'busy' state were added in this release.
When running the Layout Replication tool, an indication that replication data is loading, with the possibility to cancel out of the process, appears before opening the PCB Layout Replication dialog.
After clicking the Replicate button in the PCB Layout Replication dialog, the cursor indicates 'in progress' ( ) before the first block is placed (or ready for placement in interactive mode).
Constraint Manager Improvements
Added Support for Importing Design Directives (Open Beta)
You can now import constraints from design directives, placed and defined on your schematic source documents, into the Constraint Manager . This is performed from the Physical or Electrical view (when accessing the Constraint Manager from a schematic) using the new Import from Directives command (from the right-click context menu) and supports rule, net class, diff pair, and diff pair class directives.
Note that any existing constraints already defined for nets/net classes/diff pairs/diff pair classes through the Constraint Manager will take precedence and are, therefore, kept when an import is processed.
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Javascript ID: CM_ImportDirectives_AD24_3
On a schematic, some Parameter Set and Differential Pair directives are placed. These directives define a diff pair, a net class and Width rules.
Use the Import from Directives command from the right-click menu in the Constraint Manager .
The data from the directives will be imported into the Constraint Manager .
This feature is in Open Beta and available when the
ConstraintManager.ImportFromDirectives
option is enabled in the
Advanced Settings dialog .
New 'Diff Pairs' Tab
A new Diff Pairs tab is now available from the Electrical constraints view for explicitly defining and managing differential pairs. A hierarchical list of the differential pairs in the design is shown on this tab. Select a cell for a differential pair or differential pair class to present constraints for it in the bottom region of the Constraint Manager .
Support for Creepage in the Clearance Matrix
A Creepage rule can now be specified when defining electrical clearances between classes of nets and/or differential pairs using the matrix in the Clearances view.
Support for Multi-editing in the Clearance Matrix
Added support to the clearance matrix (the Clearance view) for multi-editing within a selected row/column. In the detailed clearance settings of the Constraint Manager , select a row or column, type the required value, and press Enter or click to apply this value to all cells of the row/column.
Draftsman Improvement
Ability to Change the Resolution of a Board Realistic View
The resolution for a placed Board Realistic View can now be configured in the Resolution(DPI) field in the Properties region of the Properties panel by entering the desired resolution in the field. Previously, the view was a static rendered image with no way to change the resolution. The minimum setting is 75 DPI, and the default setting is 300 DPI.
Harness Design Improvements
Cavity Enhancements
Specifying Cavity Types
You can now specify the type of cavity for each pin of a harness component in the Wiring Diagram (*.WirDoc
). On the Cavities tab of the Properties panel, select the desired pin, then click Add . Choose the cavity type from the drop-down. In the Select Connector dialog that opens, select the specific desired connector for the pin.
Only one cavity of a particular type can be added to a pin. Once a cavity of a particular type has been added, the entry is unavailable (grayed out) in the drop-down, as shown in the image below for Pin 3.
Added New Cavity Types to Wiring List and Connection Table
Seals, plugs and other cavity parts can be displayed in a wiring list and connection table in a manufacturing drawing. Enable the visibility of the desired columns in the Columns tab of the Properties panel when the placed table is selected in the design space.
Added Cavity BOM Line Numbers to Callouts on the Manufacturing Drawing
When a callout set to display the BOM Item is added to the physical view of a component on a layout drawing view, it will include BOM line numbers for all assigned cavities.
Visibility and Lock Options for Harness Bundle Length Parameter
The Length parameter of a harness bundle in a Layout Drawing (*.LdrDoc
) now includes visibility and lock options.
Highlight Bundles with Wires from Split Cables
All harness bundles that include wires from a split harness cable are now highlighted on the Layout Drawing when the cable is selected in the Bundle Objects region of the Properties panel. For a split cable, the length of the longest wire is shown in BOM.
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Javascript ID: HD_SplitCable_AD24_3
Cable C1
is split between different connectors.
When clicking the cable entry in the Bundle Objects region of the Properties panel for the selected bundle, all bundles that include wires from C1
are now highlighted.
In BOM, the length of the longest wire (a wire that passes through bundles B1
and B3
in this example) is shown for C1
.
Added Twist Object Designator to the Wiring List
The designator of a twist object is now displayed in the wiring list as shown in the image below.
Board Detail View Renamed Harness Detail View
The Board Detail View in a Harness Draftsman document (*.HarDwf
) has been renamed Harness Detail View .
Display Individual Wire Lengths in Wiring List and Connection Table
The Length column in a wiring list and connection table now displays the individual wire lengths for each wire in a cable.
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Javascript ID: HD_IndividualWireLength_AD24_3
Wires W1
, W2
and W3
are part of a cable.
Individual lengths of these wires are now shown in a wiring list and connection table.
Display Total Length of Wires and Cables in BOM
For harness wiring components , the Length column in the ActiveBOM document and BOM Table in a manufacturing drawing now presents the total length for wires/cables of the same BOM item rather than their individual lengths.
Data Management Improvements
Support for Custom Pricing
When you have a configured connection to a specific supplier account through the browser interface of your Altium 365 Workspace (learn more ), you can now see custom pricing where applicable in the ActiveBOM and all places where part choices are accessed. Also, suppliers that provide custom prices are labeled as such in the Project Part Providers Preferences dialog, which can be accessed by clicking the Edit button in the Favorite Suppliers List field in the Properties panel for the ActiveBOM document.
Added BOM Checks for SiliconExpert Parameters
Support for a range of checks based on SiliconExpert parameters was added to ActiveBOM. You can enable or disable these checks in the Violations Associated with Part Choices category in the BOM Checks dialog. Open the dialog by clicking the button in the BOM Checks region of the Properties panel.
When exporting comments to PDF, the status for resolved simple comments (i.e., those not assigned as 'tasks') is now included in the export.
Added Compiled IntLib to Downloaded Manufacturer Part Zip
When downloading a component from the Manufacturer Part Search panel as a file library, the compiled Integrated library (*.IntLib
) is now included as part of the Zip file.
Import/Export Improvement
Xpedition Library Import Enhancements
This release adds the following improvements when importing an Xpedition library into Altium Designer.
Added support for 'Round Donut' pad shapes defined in footprints within an Xpedition library. Note that this first step enables such footprint pads to be imported (as custom pad shapes). There is no dedicated ‘Round Donut’ pad shape in PCB/PCB Footprint editors.
Defined pad hole tolerances are now included when importing an Xpedition library.
Added support for replicated text strings in footprints (i.e., mounting hole 'A's) when importing an Xpedition library. The original string, its replicates, and associated parameters are imported.
Added support for zero-width lines defined for a footprint on the Placement Outline layer when importing an Xpedition library.
Circuit Simulation Improvements
Simulation S-Parameters Analysis (Open Beta)
This release adds the ability to run an analysis of S-parameters (scattering parameters). Such parameters facilitate an approach for describing networks based on the ratio of incident and reflected microwaves (for a device under test, how much power passes from one port to another, and how much power is reflected back). These ratios can be subsequently used to calculate the properties of a circuit, including input impedance, frequency response and isolation. While this type of analysis is primarily for RF circuits and components, it is equally useful for any circuit with at least two sources (ports).
This new analysis is done by enabling the S-Parameters Analysis option in the AC Sweep region of the Simulation Dashboard panel. Define the ports (sources) involved and set an impedance for each (default is 50 ohms). If a device has more than two ports, these can be added and defined accordingly, which will result in more S-parameters involved in the resulting ‘S-matrix.’ Once the AC sweep analysis is run, the S-parameters data will be available on the S-parameters Analysis chart in the SDF document.
The simulation engine also calculates Y-parameters (admittance) and Z-parameters (impedance), which can be added to plots in the chart as desired.
This feature is in Open Beta and available when the
Simulation.SParametersAnalysis
option is enabled in the
Advanced Settings dialog .
Added Ability to Present SPICE Models in the Components Panel
In this release, a new Show in Components Panel option has been added to the Simulation – General page of the Preferences dialog. When this option is enabled, the SPICE Libraries category is available in the Components panel, and the libraries contained in the Model Path folder specified on the Simulation – General page of the Preferences dialog are listed in this category. The category structure reflects the structure of the specified folder.
As part of this, a folder of Analog Devices' SPICE models has been added to the Mixed Simulation extension's default installation Library
folder (\ProgramData\Altium\Altium Designer <GUID>\Extensions\Mixed Simulation\Library\SPICE Models\Analog Devices
).
Added Enable Simulation Generic Components Library Option
A new Enable Simulation Generic Components Library option has been added to the Simulation – General page of the Preferences dialog, allowing you to control the library’s visibility within the Components panel.
In addition, the library has been removed from the Installed tab of the Libraries Preferences dialog .
Added Support for the 'TEMP' Keyword in Constant Parameters
For temperature analysis, the keyword TEMP
can now be used in constant parameters.
The keyword TEMP
can be used in constant parameters. The image shows the TEMP
keyword being used to calculate the IS
parameter of transistor Q11
.
The TEMP value (the actual operating temperature of the circuit in °C) is set on the Advanced tab of the Advanced Analysis Settings dialog accessed by clicking Settings in the Analysis Setup & Run region of the Simulation Dashboard panel.
Note that if the
TEMP
keyword is used in a constant parameter, the simulator will not be able to perform a
DC Sweep analysis when the
Temp parameter is selected as a parameter to be stepped for this analysis.
Added Support for the LTspice 'AKO' Model Keyword
When creating a model based on another model, you can now use the AKO
model keyword.
In the example shown below, model QP
has all the same parameters as model QP350
, except that BF
is changed and VA
is set.
.MODEL QP350 PNP(IS=1.4E-15 BF=70 CJE=.012P CJC=.06P RE=20 RB=350 RC=200)
.MODEL QP AKO:QP350 PNP(BF=150 VA=100)
Error detection is applied when using the AKO
syntax, in cases where the model definition involves:
Features Made Fully Public in Altium Designer 24.3
The following features are now officially Public with this release:
Altium Designer 24.2
Released: 15 February 2024 – Version 24.2.2 (build 26)
Release Notes for Altium Designer
Key Highlights
PCB Design Improvements
Added the Ability to Choose Components Manually while Replicating
This release extends the functionality of the PCB Layout Replication tool with the ability to manually map components in target blocks where multiple components have been detected by the tool as having similar connections. This allows you to manually choose between available components that are able to replace each other faithfully without violating circuit connectivity.
When multiple components with similar connections are detected by the tool, corresponding target blocks in the PCB Layout Replication dialog will have the icon (when the block is collapsed), and each component with available replacements will have the icon (when the block is expanded). Use the drop-down in the Designator field of the component with detected replacements to choose the required component.
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Javascript ID: Dlg_PCBLayoutReplication_Alternate_AD24_2
Added Differential Pair Common Mode Impedance in Layer Stack Manager
When Differential is selected as the Type in the Properties panel to define an Impedance Profile for a differential pair, a field has been added that shows the common mode impedance for the selected Impedance Profile. This value, which is displayed as Impedance (Zcomm) , is taken from Simbeor's calculated transmission line data.
Use of Tuning Miter Parameter for Connecting an Accordion to a Route
When interactively tuning the length of a route by adding an accordion, the Miter parameter defined for the accordion in the Properties panel is now also used to miter the traces that connect the accordion to the route. Previously, the Miter Ratio parameter defined for the interactive routing was used for these traces.
The Miter value from the accordion properties is now also applied to traces connecting that accordion to the route.
Constraint Manager Improvement
Enhanced Ability to Transfer Constraints from PCB to Schematic
In this release, the ability to transfer constraints defined on the Physical and Electrical views of the Constraint Manager has been added. In the PCB editor, select the Design » Update Schematics in <PCBProjectName> command from the main menus and use the Engineering Change Order dialog that opens to explore, validate and execute the changes in constraints.
Multi-board Design Improvement
Added Bookmarks Panel for Multi-board Draftsman Documents
The Bookmarks panel is now available in Draftsman when working with a manufacturing drawing of a multi-board design (*.MbDwf
). The panel gives a tree view of the sheets on the Draftsman document. Each sheet entry can be expanded and collapsed; when expanded, the appropriate contents of each sheet are displayed as shown in the image below.
You can use the panel to easily navigate in the design space. When an item is selected in the panel or design space, the Properties panel (if open) displays the properties and settings of the selected item. Additionally, when you select an item in the Bookmarks panel, the design space zooms to the selected item.
Harness Design Improvements
Duplicate Designator Violation Removed for Cable, Shield and Twist Objects
On the Wiring Diagram, the Duplicate Designator (WD) violation check does not report an issue when Cable/Shield/Twist objects use the same designator. This can now be split and used in different places using the same designator.
Highlight Wires for Twists and Shields
If a twist/shield is associated with wires in multiple places on the Wiring Diagram (using the same designator), selecting a twist/shield instance will highlight all associated wires in the group with a neon green color.
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Javascript ID: Harness_WD_Highlight
An example of a Wiring Diagram where two twists with the same designator are placed on different groups of wires. While only one of these twists is selected, all wires covered by these twists are highlighted.
An example of a Wiring Diagram where two shields with the same designator are placed on different groups of wires. While only one of these shields is selected, all wires covered by these shields are highlighted.
Added Support for Multi-part Components
The ability to transfer multi-part component data from the Wiring Diagram to the Layout Drawing has been added. When multi-part components are placed on the Wiring Diagram, designators are correctly assigned to the components in the Layout Drawing. If multiple parts of the same component are placed on the Wiring Diagram, only one instance of the component is placed on the Layout Drawing.
Added Support to Connect Shields to a Connection Point
A shield with a connection object that is defined on the Wiring Diagram can now be assigned to a connection point in the Layout Drawing. Use the Add Assigned Objects dialog (accessed by clicking the Add button in the Assigned Objects region of the Properties panel) when the connection point is selected to choose the shield with a connection to be assigned to that connection point.
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Javascript ID: Harness_ShieldConnection_CP
Added Support for Multicolored Wires
Multicolored wires are now supported in the Wiring Diagram by choosing a wire's secondary and tertiary colors. (The primary color is the color of the placed wire.) In the Properties panel, click the Add drop-down at the bottom of the Parameters region then choose Secondary and Tertiary to define the desired colors; the parameter for the chosen color will appear in the Parameters region. Click the color icon in the panel to open the color options; click the desired color. You can also define the border color for the wire using the same drop-down then selecting Border . Click through the slideshow below for examples.
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Javascript ID: MultiColorWire
Wire with the secondary color defined
Wire with the tertiary color defined
Wire with the border color defined
Wire with all color options defined
Multicolored wires are also supported in harness design Draftsman documents (*.HarDwf
). Additional columns for secondary, tertiary and border colors can be made visible in placed tables, and corresponding Color cells are split to show the secondary and tertiary colors assigned to the wire.
Added Support for Multiple Wiring Diagrams in Draftsman Documents
The Harness Draftsman document (*.HarDwf
) now supports multiple Wiring Diagram documents (*.WirDoc
) in the same project. This feature lets you choose the wiring diagram document from which a placed wiring diagram view should be generated and updated. Use the Document drop-down in the Properties region of the Properties panel when the wiring diagram view is selected to choose the wiring diagram document for this view.
Added Bookmarks Panel for Harness Draftsman Documents
The Bookmarks panel is now available in Draftsman when working with a manufacturing drawing of a harness design (*.HarDwf
). The panel gives a tree view of the sheets on the Draftsman document. Each sheet entry can be expanded and collapsed. When expanded, the appropriate contents of each sheet are displayed as shown in the image below.
You can use the panel to easily navigate in the design space. When an item is selected in the panel or design space, the Properties panel (if open) displays the properties and settings of the selected item. Additionally, when you select an item in the Bookmarks panel, the design space zooms to the selected item.
Data Management Improvements
SiliconExpert Enhancements
Added SiliconExpert Product Change Notice
The Product Change Notice (PCN) provided by SiliconExpert has been added to the Manufacturer Part Search panel and to all places where part choices can be accessed. By default, the latest PCN data is shown. Use the Historical Details control to open the Product Change Notice Historical Details dialog, where details on previous PCNs can be browsed.
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Javascript ID: SE_PCN
Access the latest and historical PCNs from the Manufacturer Part Search panel.
Access the latest and historical PCNs from a part choice (the Components panel is shown as an example here).
Added SiliconExpert 'Free' Parameters Support
The Lifecycle , YTEOL and RoHS Status parameters provided by SiliconExpert are now presented by default in the Manufacturer Part Search panel and all places where part choices are presented. Therefore, there is no need to request data for this part (and hence, use the quota from your SiliconExpert package) to access these 'free' parameters.
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Javascript ID: FreeSEParameters_AD24_2
Access 'free' parameters provided by SiliconExpert from the Manufacturer Part Search panel.
Access 'free' parameters provided by SiliconExpert from a part choice (the Components panel is shown as an example here).
Also, these SiliconExpert 'free' parameters can be used in ActiveBOM (by adding corresponding columns to the ActiveBOM document) without requesting all other SiliconExpert parameters.
Added Display of the YTEOL Parameter
The YTEOL parameter is now displayed in the following locations:
In the header of the Details pane when a manufacturer part is selected in the Manufacturer Part Search panel.
In the header of the Details pane when a component is selected in the Components panel.
In all places where part choices are presented.
In the Properties panel when a component placed on a schematic sheet is selected.
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Javascript ID: SE_YTEOL_AD24_2
Displaying the YTEOL parameter in the Manufacturer Part Search panel.
Displaying the YTEOL parameter in the Components panel and in part choices.
Displaying the YTEOL parameter in the Properties panel for the selected component.
Added Support for SiliconExpert Parameters when Comparing Manufacturer Parts
SiliconExpert parameters are now supported in the Selected Part Details pane of the Manufacturer Part Search panel when comparing two selected parts.
Added Support for Aggregated Lifecycles to Manufacturer Links
When exploring a solution added in the form of a manufacturer link to an ActiveBOM document if there are multiple sources of the lifecycle data for that manufacturer link (Altium Parts Provider powered by Octopart or IHS Markit® and SiliconExpert), the lifecycle information from all available sources is now accessible for the link. Hover the cursor over the manufacturer lifecycle state or use the drop-down to see the lifecycle information from all sources in the tooltip/pop-up.
Import/Export Improvement
For an Xpedition library (*.lmc
) whose schematic symbols (only) were previously imported using the xDX Designer Import Wizard with the Import Symbols Only option enabled, you can now choose to import footprint models into a PCBLib as part of the existing project structure. Footprints will be renamed in accordance with the naming defined in the existing CSV file generated as part of the xDX Designer import process.
Note that starting from this release, footprint names with specific prefixes (BGA
, CAP
, CAPC
, CGA
, COUP
, DFN
, DIO
, DR
, FILT
, FUSE
, INDC
, INDM
, ISOL
, LEDC
, LEDS
, LGA
, MECM
, OSC
, PQ
, PS
, QFN
, QFP
, RESC
, RESM
, SO
, TO
, VAR
, XTA
) will include the component height values multiplied by 100 in the generated CSV files to provide unique naming of footprints with differing 3D Body heights. For example, a footprint of height 1.4
and named CAPC2013N
will be added to the CSV file as CAPC2013X140 N
.
When adding an Xpedition library file on the Importing Mentor Expedition Library Files page of the Import Wizard , if previously imported libraries are detected, a confirmation dialog will ask if you would like to import footprints as described above. If you click No , footprints will be imported into a separate folder for generated PCBLib files, and no footprint renaming will be performed.
Feature Made Fully Public in Altium Designer 24.2
The following feature is now officially Public with this release:
Altium Designer 24.1
Released: 16 January 2024 – Version 24.1.2 (build 44)
Release Notes for Altium Designer
Key Highlights
Schematic Capture Improvement
Added Violation Checks for Objects Connected to a Harness Connector
In this release, new violation checks have been added to detect violations associated with signal harnesses in the schematics of your PCB design projects:
The Invalid Connection to a Harness Connector violation check detects a situation when a wire, bus, or signal harness ends inside or is connected to the edge of a harness connector but is not connected to a harness entry.
The Unconnected Harness Entry violation check detects an unconnected harness entry.
Settings for these violation types can be found in the Violation Associated with Harnesses group on the Error Reporting tab of the Project Options dialog .
PCB Design Improvements
Pad Hole Clearance Check Improvement (Open Beta)
In this release, the behavior of detecting clearance from pads with no annular ring has been improved.
When a pad has a hole size greater than or equal to the pad size and, therefore, has no annular ring, the clearance value defined for the Hole by the applicable constraint in the Constraint Manager or by the Clearance design rule is applied rather than the maximum of Hole and TH Pad clearances.
An example of clearances configured in the Constraint Manager .
An example of clearances configured in the Clearance design rule.
The new pad hole clearance behavior.
Note that the default values of Hole clearance in newly created Clearance constraints and Clearance design rules have been updated with the 10mil
/ 0.254mm
value.
This feature is in Open Beta and available when the
PCB.Rules.HoleClearance
option is enabled in the
Advanced Settings dialog .
Ability to Store TrueType Fonts (Open Beta)
This release has added the ability to automatically store geometries of text objects that use TrueType fonts inside PCB documents. When objects (text strings/frames, dimensions, drill tables, and/or layer stack tables) in a PCB document use a TrueType font, these objects will be shown using the same font geometry when the PCB document is opened on another computer, even if that TrueType font is not installed.
When an object that uses a missing font is selected, a warning message appears at the top of the Properties panel. When changing object properties that affect its text (e.g., the text height or text itself), the Missing fonts dialog opens in which you can select a replacement font.
The dialog also appears when changing text-related properties from the PCB List panel.
When trying to edit multiple objects using different missing fonts, the dialog allows you to select a replacement for each missing font.
This feature is in Open Beta and available when the PCB.Text.TTFontSaving
option is enabled in the Advanced Settings dialog .
Note that with this feature enabled, the options of the PCB Editor – True Type Fonts page of the Preferences dialog are no longer relevant, so this page is not available in the Preferences dialog (when the PCB.Text.TTFontSetting.Hide
option is enabled in the Advanced Settings dialog ).
Enhanced Pad Properties Panel
The Pad Stack region of the Pad Properties panel has been enhanced for better usability. When a section is selected, the section name is highlighted in blue and the entire section is displayed in a different shade than the background.
PCB CoDesign Improvements
Ability to Highlight Category Changes
With the Show on PCB option enabled in the PCB CoDesign panel, you can now highlight all changes in a specific category when that category is selected in the panel's list of changes.
Grouping Changes by Unions
Added support for comparison of, and application of changes to, unions (defined groupings of primitives on the PCB). Union-related changes are shown in the Unions category in the PCB CoDesign panel's list of changes. Also, changes in other categories are grouped now by unions if corresponding objects belong to any.
Updates to 'Merged' State
After merging changes using the PCB CoDesign panel, the PCB document will remain in the Merged state (the icon in the Projects panel) until there is a new conflict. Saving changes locally will no longer change the state to Modified .
Also, note that documents in Merged state are always enabled for saving to the Workspace in the Save to Server dialog and cannot be disabled.
Constraint Manager Improvements
Ability to Choose Usage of the Constraint Manager for a New Project
When creating a new PCB project, you now have the ability to control whether it will use the Constraint Manager or the older design rules system. In the Create Project dialog (File » New » Project ), enable the Constraint Management option to use the Constraint Manager for the project being created.
'View Only' Mode
If the Constraint Manager was enabled for the PCB project, the Constraint Manager will present in View Only mode when opened by a user without Altium Designer Pro/Enterprise Subscription. In this case, the user can see, but not modify, defined constraints. The message at the top of the Constraint Manager notifies you when the Constraint Manager is in View Only mode.
Updates to xSignal Creation
This release sees some updates in defining xSignals using the Constraint Manager :
The list of proposed xSignals is now divided into two groups: xSignals going from a source to a destination point (S-T ) and xSignals going from one destination point to another (T-T ). Use checkboxes for groups to select/deselect all xSignals in corresponding groups.
The list of proposed xSignals now includes xSignals going from a source to each destination (not an xSignal going from a source to the closest destination only).
For a better representation of proposed xSignals, they are now named in the list using the following scheme:
<SourceNetName> (<SourcePinDesignator> → <DestinationPinDesignator> )
Note that for names of created xSignals that can be seen on the xSignals tab to the Constraint Manager or in the PCB document, the previous <SourceNetName> _<SourcePinDesignator> _<DestinationPinDesignator>
scheme is used.
Improved Class Selection
The right-click menu of entries in the Physical and Electrical views has been updated to quickly add objects to an existing class right from the menu. To do this, right-click one or more selected objects and choose an existing class from the Classes » Add Selected to Class sub-menu.
When there are more than 30 classes, the Classes » Add Selected to Class » Existing Class command is available in the menu instead of the list of classes. Use this command to access a dialog where you can select an existing class to which the selected object(s) are to be added.
Added Line Numbers in Grid
Line numbers have been added to the Constraint Manager grid to help you more easily identify and distinguish items in the list.
Multi-board Design Improvements
Support for Draftsman Documents in Multi-board Projects (Open Beta)
You can now add a Draftsman document (*.MbDwf
) to a Multi-board project to create a manufacturing drawing for the Multi-board assembly in this project.
The views that can be placed in a Draftsman document of a Multi-board project are:
Multi-board view – an automated graphic composite of the outlines of PCBs and 3D models constituting the multi-board assembly.
Section view – a profile slice, or sectional, drawing taken from a nominated 'cut' point through a placed multi-board view.
Board detail view – a floating, magnified view of a multi-board view's defined area.
Board realistic view – a scalable 3D rendering of the current multi-board assembly.
Draftsman's annotation, dimensioning and graphical tools, as well as BOM and generic tables, are also available.
An example of a Multi-board project Draftsman drawing.
Ability to Move a Module Entry Group
The ability to move a selected group of module entries in a multi-board schematic document (*.MbsDoc
) has been added. This new feature speeds up the editing process by not requiring you to move each module entry individually. In the design space, select more than one module entry, then use the left mouse button to drag the group to the desired location. A red dot displays at each entry while they are dragged to the new location. Release the mouse button to place the group at the current location.
Harness Design Improvements
Changed 'Crimps' to 'Cavities'
'Crimps' have been renamed 'Cavities' in the UI of the Wiring Diagram and Layout Drawing.
Added Designator Field to Shield and Twist Objects
The Designator field has been added to the properties of shields and twists in the harness wiring diagram.
Added Wire Break Object for Multiple Sheet Capability
A full Wiring Diagram can now be defined over multiple sheets (in a 'flat' design fashion), each represented by its own *.WirDoc
document, with the ability to split a wire using the new Wire Break object.
A Wire Break is placed using the Place menu or from the Active Bar as shown below.
Treat Coverings as Components in BOM
Harness coverings in the Layout Drawing are now treated as components in the BOM, with support for part choices and grouping.
Display Component Properties for Additional Physical Views
When an additional physical view of a harness component is selected in the design space, the Properties panel now displays the properties of the component itself as it does for the main (first) physical view. In the below image, a second physical view has been selected in the design space; the Harness Component Properties panel displays the properties of the original (first) physical view.
Improved the Wiring List
Added Ability to 'Split' Wiring List
The wiring list of an advanced harness design may have a large number of entries, which can be difficult to fit into a drawing document as a single table. Rather than resorting to font and table scaling, multiple custom table entries, or an external document, you now have the ability to 'split' a Wiring List in a Harness Draftsman document so that the Wiring List will be presented over a number of 'pages.' In the Properties panel for a placed Wiring List, enable the Limit Page Height option in the Pages region to use the new feature. This will restrict the height of the Wiring List table to the nominated height entry (Max Page Height ) and, therefore, the number of lines shown in the table.
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Javascript ID: Harness_MD_WiringList_LimitPageHeight
The editor detects that the entire Wiring List is not shown, as indicated by the panel's Page entry (for example, 1 from 2
), and the associated drop-down menu allows you to nominate which page is shown. To add further pages of the Wiring List, place another Wiring List (Place » Wiring List ) and specify the next Page in the Pages region of the Properties panel.
Enhanced Wiring List for 'Shield with Connection' Objects
Designators of shield with connector objects are now displayed in the Wiring List when a wire is connected to the shield's connector.
Added Ability to Display Connection Table for Splices
The ability to show the connection table for individual splices has been added. Previously, the ability to show the Connection Table for only components and connectors was possible.
Links Added to Text Frame and Note Objects for Cross-Probing
Object designators can now be added as active links in text frames and notes. The links provide cross-probe capabilities in the Wiring Diagram and Layout Drawing. To create active links, place a text frame or note object in either the Wiring Diagram or Layout Drawing. In the Text field in the Properties region of the Properties panel, enter "@". A drop-down of all designators will appear. Double-click the desired designator from the li st; the link is created in the Text field and in the design space. Click the link in the design space to cross-probe to that object in the associated document (i.e., the document that is not currently active). The process is demonstrated in the video below.
Data Management Improvements
Manufacturer Lifecycle State Message Enhancement
When using the SiliconExpert integration functionality, manufacturer part lifecycle data can be obtained from different sources: Altium Parts Provider (powered by Octopart or IHS Markit® ) and SiliconExpert . To provide better visibility of this lifecycle data from different sources, the lifecycle information from all available sources is now accessible.
When exploring manufacturer part data (e.g., an entry in the Manufacturer Part Search panel , a part choice of a Workspace library component, or a solution in an AcitveBOM document ), hover the cursor over the manufacturer lifecycle state/bar or use the drop-down to see the lifecycle information from all sources in the tooltip.
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Javascript ID: ManufacturerLifecycle_MultipleSources_AD24_1
Added General Tab to Project Options for Offline Workspace Projects
Added the General tab to the Project Options dialog for offline Workspace projects. This feature is available for working with a project when you are disconnected from its Workspace. The only control on the tab that is accessible is the Turn Off Synchronization button. Click this button to turn off synchronization. This ensures that the local copy will not be linked to the one that resides on the Workspace. The project located in the Workspace will remain untouched.
Removed Commit Command for Git-based Projects
For Git-based projects, the Commit command has been removed from the History & Version Control sub-menu of the right-click menu of project entry in the Projects panel and the Project main menu, aiming to remove confusion about where data was being committed (to the local repository and not the remote repository) when using the command. Visibility of the command is controlled by the VCS.AllowGitCommit
option from the Advanced Settings dialog (OFF by default). You can use the Save to Server command to commit the project to the local repository and push it to the remote repository in one action.
Import/Export Improvement
Mentor Xpedition Placement Outline and Insertion Ouline Layer Mapping
When Mentor Xpedition PCB and footprint library files are imported, Placement Outline layer types are now mapped as Courtyard layer types and the Insertion Outline layers are now mapped to the Component Outline layer types in Altium Designer.
Circuit Simulation Improvement
Simulation Stress Analysis (Open Beta)
Stress Analysis is used to calculate operating conditions for each individual component, such as maximum voltages, currents, and power dissipations, and check them against limits defined in the stress model of the component.
In this release, a new Stress Analysis option has been added to the Transient region of the Simulation Dashboard . When this option is enabled and the Transient analysis is performed, the Stress analysis results are available on the additional Stress chart of the simulation result document.
Use the new Stress Analysis to test your circuits against defined limits.
The stress model of a component is configured on the new Stress tab of the Sim Model dialog accessed for the component's simulation model. From here, you can select the required Device Type and define parameter values.
Stress analysis parameters for a component can be set on the Stress tab of the Sim Model dialog.
This feature is in Open Beta and available when the
Simulation.StressAnalysis option is enabled in the
Advanced Settings dialog .
Feature Made Fully Public in Altium Designer 24.1
The following feature is now officially made Public with this release:
Altium Designer 24.0
Released: 13 December 2023 – Version 24.0.1 (build 36)
Release Notes for Altium Designer
Key Highlights
PCB Design Improvements
Any Angle Diff Pair Router (Open Beta)
This release introduces support for any angle differential pair routing. When routing a diff pair using the Interactive Differential Pair Routing tool (Route » Interactive Differential Pair Routing ), you can now select the Any Angle corner style ( ) when configuring the properties of routing in the Properties panel in its Differential Pair Routing mode.
Any angle differential pair routing supports symmetrical pad entry and gap changing.
When starting differential pair routing from an antenna, the tool will maintain the left-to-right order of nets (i.e., the continuation of the left side stays on the left) and support snapping to the original direction.
When routing a diff pair using the Any Angle corner style, press and hold the Shift key to route the diff pair using tangent arcs.
Demonstration of any angle differential pair routing.
Note that this feature also enables an updated angle diff pair glossing algorithm when using the Route » Gloss Selected command.
The current main limitations of any angle diff pair routing are:
Routing transitions through borders of rooms with different design rules are not currently supported.
The SMD Entry design rule is not currently supported.
Automatic loop removal is not currently supported.
This feature is in Open Beta and is available when the
PCB.Routing.AnyAngleDiffPairRouter
option is enabled in the
Advanced Settings dialog .
Enhanced Layer Stack Report Setup Dialog (Open Beta)
The Layer Stack Report Setup dialog (File » Fabrication Outputs » Report Board Stack ) has been enhanced and now includes all columns that are present in the Layer Stack. Use the dialog to select the columns you want to be displayed in the Layer Stack Report.
This feature is in Open Beta and available when the
PCB.ModernBoardStackGenerator
option is enabled in the
Advanced Settings dialog .
PCB CoDesign Improvements
Enhanced Copper Conflict Display and Resolution
Conflicts of copper objects are now grouped in pin-to-pin connection groups where applicable to ease exploring and resolving the changes.
Copper conflicts can now be resolved on the pin-to-pin connection level.
In the View Configuration panel , you can now select colors for objects that have been added, modified, removed, and not changed (unchanged objects of a pin-to-pin connection when it is selected in the PCB CoDesign panel).
Use the View Configuration panel to configure the comparison color legend.
Other PCB CoDesign UI Changes
The pop-up that shows that the comparison is in progress now appears right after running the comparison.
Added the ability to select and deselect entries in the change list. When an entry is selected (by clicking on it), click it again to deselect the entry and reset the object highlighting in the design space.
The Save to Server command has been added to the menu of the Project panel's Merged icon ( ) shown after merging changes using the PCB CoDesign panel – show image .
When clicking the Save to Server button in the PCB CoDesigner panel after merging changes, only the merged PCB document is selected in the Save to Server dialog by default – show image .
When merging the changes is run, a new pop-up showing that merging is in progress is now displayed – show image .
Constraint Manager Improvements
Ability to Add Differential Pair Classes to the Clearance Matrix
Starting from this release, you can add not only net classes but also differential pair classes to the Clearance Matrix (the Clearances view).
Editing Custom Topology on the PCB Side
It is now possible to define the topology of a net as Custom and edit it as required in the Constraint Manager when it is accessed from the PCB side.
Propagating Topology Changes when Editing the Constraint Set
When editing a Constraint Set that includes a custom topology, changes made to the topology are now propagated to other objects to which this Constraint Set is applied.
Ability to Remove xSignals
It is now possible to remove an xSignal from the xSignals tab of the Electrical view. To do this, right-click an xSignal and select the xSignals » Remove xSignal command from the context menu.
Cross Select From and To the Constraint Manager
In this release, an ability to cross-select objects from and to the Constraint Manager has been added. When cross-select mode is enabled (using the Cross Select Mode command from the Tools main menu of the Constraint Manager , the schematic or PCB editor), objects selected in the Constraint Manager are also selected in the schematic and PCB documents, and vice versa.
Enhanced the Expand/Collapse State
All nodes, except for those that are predefined (e.g., All Nets ), are now collapsed in the Physical and Electrical views by default. You can use the new Expand All and Collapse All right-click menu commands to control the grid nodes.
3D-MID Design (Open Beta)
3D-MID technology combines electrical circuits with three-dimensional mechanical parts. This fusion of functionality opens up a world of possibilities within a vast range of application areas.
Historically, designers of 3D-MIDs have generally been restricted to MCAD packages due to the lack of suitable ECAD tools. There are many problems inherent to this way of working, not least is the absence of any electrical intelligence to drive the circuit layout and the difficulties associated with projecting 2D manually drawn sketches onto 3D surfaces.
The new 3D-MID editor in Altium Designer allows you to place standard surface mount components onto a 3D shape in a 3D-MID document and route traces along the surface of the shape to complete the layout.
The completed design can then be exported in the file format required by the Laser Direct Structuring (LDS ) manufacturing process.
Note that the 3D-MID functionality is not supported with the Altium Designer Standard Subscription. If you are interested in 3D-MID and have a Standard Subscription, talk to your Altium sales representative about your evaluation options.
Harness Design Improvements
Treat Layout Labels as Components in BOM
Layout labels in the Layout Drawing are now treated as components in the BOM, with support for part choices and grouping.
Added Columns to the Connection Table and Wiring List
Additional columns have been added to the Connection Table and Wiring List in a Manufacturing Drawing (*.HarDwf
) that allow you to easily view the additional information in the design space. Crimp (part number), Cable , ToPin , and ToPart have been added to the Connection Table; FromCrimp , ToCrimp , and Cable have been added to the Wiring List. Toggle the eye icon in the Properties panel to display/hide the desired columns in the connection table.
Support for Long Path Names (Open Beta)
Support for long path names has been implemented in this release. When a file path with the file name exceeds 256 characters, the actions on files are now supported, including:
Opening a project from the connected Workspace.
Making a local project available in the Workspace.
Changing the folder path in an Outjob file.
Generating outputs using an Outjob file or the Project Releaser .
Saving a project as a project template to the Workspace.
Starting from Windows 10 version 1607, MAX_PATH limitations have been removed from common Win32 files and directory functions. However, you must opt-in to the new behavior by changing a registry key on the computer where Altium Designer is installed. Refer to the Support for Long Path Names page for details. After doing so, ensure that your computer is rebooted.
WARNING: Modifying the registry improperly can result in Windows becoming unusable. Use the Registry Editor only at your own risk and only after backing up the registry as outlined in the Microsoft article
How to back up and restore the registry in Windows .
When releasing a project that uses a long path to an Enterprise Server Workspace, the PC where the Altium On-Prem Enterprise Server is installed should also be configured:
learn more .
This feature is in Open Beta and is available when the
System.LongPathsSupport
option is enabled in the
Advanced Settings dialog . Note that this option is available only when the
LongPathsEnabled
registry key is set to
1
.
Import/Export Improvements
xDX Designer Import Enhancements
This release delivers a number of key improvements and fixes in relation to the import of xDX Designer design files into Altium Designer.
Added Ability to Import Symbols Only
The Reporting Options page of the Mentor xDxDesigner Import Wizard now includes the Import symbols only option that allows to import symbols only. When this option is enabled, identical symbols from the library database will be imported as a single schematic symbol, even if it is used by many components in the original library, and parameters are not imported to symbols in Altium Designer.
Also, when this option is enabled, the next page of the Wizard will suggest generating part-symbol and pin mapping data in CSV format by enabling the Generate Pin Mapping and Component Models/Parameters Combined CSV option. When this option is enabled, use the available fields to define Oracle DB connection parameters and a parameter mapping file.
Multi-part Symbol Import Improvements
When imported to Altium Designer, a multi-part symbol receives a Design Item ID combined with the first and last part names defined in xDX Designer. These combined Design Item IDs are also used in the generated CSV files.
Also, the order of parts in symbols imported to Altium Designer is now the same as defined in the original library.
Symbol Import Improvements
Other import improvements include:
Mentor Expedition Import Improvements
Added Ability to Choose Extruded Body Layer
You now have the ability to choose the layer when creating extruded bodies when importing Mentor Expedition files using the Import Wizard . After adding the Mentor PCB and Library files to be imported, choose from Placement Outline or Assembly Outline using the Create extruded body from drop-down on the Current User Layer Mappings page. When the option is enabled, the default is Placement Outline .
Placement Outline Improvement
Placement Outlines can now be imported as primitives on the Placement Outline layer on the Top/Bottom 3D Body assembly layers.
Circuit Simulation Improvement
Output Currents for P-Channel Transistors Inverted
Output currents for P-Channel transistors (BJT, JFET, MOSFET, MESFET) are now treated as inflow currents, making them consistent with N-Channel transistors.
Ansys CoDesigner (Open Beta)
This release presents the first steps into true collaborative design (CoDesign) between the ECAD and Simulation domains. Up until now, engineers in these two siloed camps have had to rely on manual export/import file processes that have no connection with a revision of a design and communication of changes and results, typically by email, outside of the design arena.
Now, with the arrival of the Ansys CoDesigner feature, the ECAD engineer (using Altium Designer) can seamlessly collaborate on a design with their SIM engineer colleague (using Ansys Electronics Desktop (AEDT)). Collaboration is facilitated through an Altium 365 Workspace, which acts as a bridge between the two domains. This initial release includes support for the following key elements:
Bi-directional push/pull of design changes between the two domains. From Altium Designer, changes to layer stack and materials, components, and primitives are detected and can be applied in AEDT. From AEDT, proposed changes to layer stack and materials can be pushed through the EDB file and detected/applied in Altium Designer.
Simulation results are pushed from AEDT to the Altium 365 Workspace and associated with a revision of the design, with the ability to view through the Workspace’s browser interface and preview within Altium Designer.
Bi-directional communication using the commenting system, with each comment thread attached to a specific component in a design.
Currently, AEDT of version 2023 R1 and 2023 R2 is supported by Ansys CoDesigner.
Note that Ansys CoDesigner is not supported with the Altium Designer Standard Subscription.
This feature is in Open Beta and is available when the
Ansys CoDesigner (for Altium Designer) and
Altium Link (for Ansys Electronics Desktop) extensions are installed. The latter can be obtained by contacting
ansyscollaboration@altium.com .
Power Analyzer by Keysight Improvement
Added Ability to Assign Currents for Multiple Nets on the Same Component
In this release, the ability to assign currents for multiple nets on the same component for different series elements has been added.
When configuring a load of the IC (Current) type, you can see all pins of the load component that connect it with the source through different serial components, with the ability to select the required pins.
In the example shown below, the 5V
power net is connected to two pins of the LCD1
component through R4
and R5
series components. After extending the power net and adding LCD1
as the load, both pins can be selected and configured as required in the Load Properties dialog.
Features Made Fully Public in Altium Designer 24.0
The following features are now officially made Public with this release: