New in Altium Designer

 

This page details the improvements included in the initial release of Altium Designer 24, as well as those added in subsequent updates. Along with delivering a range of improvements that develop and mature the existing technologies, each update also incorporates a large number of fixes and enhancements across the software based on feedback raised by customers through the AltiumLive Community's BugCrunch system, helping you continue to create cutting-edge electronics technology.

You can choose to continue with your current version, update your current version, or install Altium Designer 24 alongside your current version to access the latest features. Your current version can be updated from within the software in the Extensions and Updates view. If you prefer to install Altium Designer 24 alongside your current version, visit the Altium Downloads page to download the installer, then choose New Installation on the Installation Mode page of the installer.

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Altium Designer 24.10

Released: 10 October 2024 – Version 24.10.1 (build 45)

Release Notes for Altium Designer

Schematic Capture Improvement

Support for Empty Sub-parts in Normal Mode

Improved single/multi-part symbol handling, extending the same features and functionality available for Alternate display modes, to the Normal display mode. For example, a component can now be represented by a single symbol in the Normal display mode and by two symbols in its Alternate mode, as shown in the image below.

  • If a multi-part component only has primitives defined in one sub-part, the designator suffix is hidden when that sub-part is placed on a schematic sheet, regardless of the current display mode and which sub-parts have primitives (the first sub-part or not).

  • If a multi-part component has empty sub-parts in its view mode (either the Normal or an Alternate mode), these sub-parts are omitted during placement.

  • An Unused sub-part in component violation will not occur when running a design validation if a component has sub-parts without primitives and these sub-parts are not placed on the schematic, regardless of the display mode.

Also, it is now possible to change part or display mode to one without any primitives. A warning icon is shown next to the corresponding entries in the Properties panel when an empty sub-part or display mode is selected ().

For more information, refer to the Searching for & Placing Components page.

PCB Improvements

Wire Bonding (Open Beta)

In this release, support for designing hybrid boards with chip-on-board (CoB) technology using Wire Bonding has been added. This feature allows you to create a component with defined Die Pads (corresponding to pins of the schematic symbol). Once placed on a schematic and synchronized (through ECO) to the PCB, it can be wired to regular pads (or any copper) on the main board using Bond Wires. When connecting to a regular pad, that pad takes on the likeness of a Bond Finger pad.

You can define a complete, simple package with defined die pads, bond finger pads, and bond wires, all as part of the component footprint.

  • Support for adding die pads is provided courtesy of a predefined Die component layer pair (Top Die / Bottom Die). Note that when a die pad is placed on an extruded 3D body (also on the Top Die / Bottom Die layer), it will be automatically placed at the Overall Height of this 3D body.

  • For placement of bond wires (from die pad to bond finger pad, die pad to die pad, etc.), a predefined Wire Bonding component layer pair is provided (Top Wire Bonding / Bottom Wire Bonding). Use the Place » Bond Wire command or  on the Active Bar to place a bond wire. Use the fields in the Profile region of the Properties panel to specify the desired values of the Loop Height and Diameter of a bond wire, as well as the Die Bond Type (Ball or Wedge) – .

  • Regular pads to which bond wires are connected (bond finger pads) can be aligned with bond wires. To do this, select bond wires and bond finger pads connected to them, right-click the selection, and then choose the Pad Actions » Align Bond Finger with Bond Wire command from the right-click menu.

An example of a footprint (in 2D and 3D views) that features wire bonding.
An example of a footprint (in 2D and 3D views) that features wire bonding.

When using the Chip-on-Board approach, you can also place bond wires manually to connect the die pads of the chip to any copper on the main board. A bond wire will inherit the net of its source die pad. Multiple bond wires can emanate from the same die pad, and conversely, multiple bond wires can finish on the same copper on the main board.

An example of a PCB that features wire bonding.
An example of a PCB that features wire bonding.

A new Wire Bonding design rule has been added in the Routing category to support wire bonding and can be defined in the All Rules view of the Constraint Manager when accessed from a PCB and the PCB Rules and Constraints Editor dialog (when using the older approach to design rule definition and management). The rule enables constraints to be defined for the permissible distance between adjacent bond wires (Wire To Wire), Min and Max Wire Length, and Bond Finger Margin, which is the distance/padding between a bond wire and the edge of the bond finger pad to which it is wired. The Wire Bonding design rule is supported by the batch DRC. Electrical rule checks (Un-Routed Net and Short Circuit) also apply to Wire Bonding.

In terms of manufacturing documentation, Draftsman supports wire bonding in both its regular board assembly view (for the main Chip-on-Board approach) and also the component view (for where the wire bonding ‘package’ has been fully defined within the footprint). Wire bonding information is also supported when generating regular PCB prints.

A wire bonding table report that provides information in relation to die pads and bond finger pads can be generated (in the CSV format). Use the Wire Bonding Table Report output from the Assembly Outputs region of an outjob file to add a new output of this type, or select the File » Assembly Outputs » Wire Bonding Table Report command from the main menus of the PCB editor to generate the report.

This feature is in Open Beta and available when the PCB.Wirebonding option is enabled in the Advanced Settings dialog.

For more information, refer to the Wire Bonding page.

Phase Matching for Differential Pairs (Open Beta)

This release includes the ability to enable phase matching between the sides of a differential pair, as part of automatic diff pair length tuning.

To perform phase matching between the sides of required differential pair(s) according to the applicable Matched Lengths constraint with the Within Differential Pair Length option selected, select primitives of these diff pairs and choose the Route » Automatic Length Tuning command from the main menus. In the Auto Tuning Process dialog that opens, open a new Sawtooth tab and configure parameters of the sawtooth-based pattern as required. After clicking OK in the dialog, the sawtooth tuning patterns will be added to the sides of the differential pairs to equalize their lengths.

This feature is in Open Beta and available when the PCB.TraceTuning.PhaseTuning option is enabled in the Advanced Settings dialog.

For more information, refer to the Length Tuning page.

Dynamic Phase Matching for Differential Pairs (Open Beta)

This release brings dynamic phase matching support for differential pairs, which is an essential consideration for high-speed PCB designs. For maximum efficiency of differential signal transmission, differential pairs need to be both statically (equalizing the length of the two sides in a pair) and dynamically (matching the phase along the entire length of the pair) phase-matched. New dynamic phase matching constraints and automatic tuning with phase compensation have been implemented, to avoid time-consuming phase mismatch detection and elimination.

The Matched Length design rule has been extended with the ability to specify dynamic phase matching constraints. When the Within Differential Pair Length option is selected, a new Dynamic Phase Matching checkbox is available. When it is enabled, you can define the following constraints:

  • Dynamic Phase Tolerance / Dynamic Phase Delay Tolerance – the permissible phase mismatch between the tracks in a pair above which compensation is required.
  • Matching Distance – the distance after exceeding the tolerance, for which compensation must be applied.

Depending on if Length Units or Delay Units are selected in the rule, the above constraints are defined in millimeters or picoseconds, respectively.

Support for this enhanced rule is available in both the All Rules view of the Constraint Manager (accessed from PCB) and the PCB Rules and Constraints Editor dialog (when using the older approach to design rule definition and management).

Dynamic phase matching constraints configured in the Constraint Manager
Dynamic phase matching constraints configured in the Constraint Manager

Dynamic phase matching constraints configured in the PCB Rules and Constraints Editor dialog​​​​​
Dynamic phase matching constraints configured in the PCB Rules and Constraints Editor dialog​​​​​

Detected rule violations will be marked with a hatched pattern on corresponding traces in the design space (with the hatching starting at the detected point of phase mismatch, i.e., defined tolerance exceeded).

You can use the Automatic Length Tuning tool to eliminate violations of dynamic phase matching. Select the required diff pairs (any tracks of the diff pairs) and choose the Route » Automatic Length Tuning command from the main menus. On the Sawtooth tab of the Auto Tuning Process dialog that opens, set phase matching parameters as required and click OK to add sawtooth patterns required to provide dynamic phase matching of the diff pairs. Note that the electrical types of pads at either end of a routed diff pair are taken into account, so that if a source/load has been specified, tuning will be applied moving along the diff pair in the appropriate direction.

This feature is in Open Beta and available when the PCB.Rules.DiffpairPhaseMatching option is enabled in the Advanced Settings dialog.

For more information, refer to the High Speed Rule Types page.

Routing Topology DRC Support (Open Beta)

Implementation of custom topologies defined using From-Tos can now be checked as part of the Batch DRC process. Enable the Batch option for the Routing Topology design rule type in the Design Rule Checker dialog (Tools » Design Rule Check) to detect violations.

A violation is detected if there is an electrical connection between the pads of a From-To, and the shortest path contains at least one other pad of this net.

Javascript ID: RoutingTopology_FromTos_AD24_5

Two From-Tos are created between three pads – from pad 1 to pad 2 and from pad 2 to pad 3

Routing is created according to the configuration of From-Tos – there is routing between pads 1 and 2 and between pads 2 and 3. No violation of the Routing Topology rule is detected.

Routing is created in a T-branch manner. There are no additional pads in paths according to the From-To configuration, so no violation of the Routing Topology rule is detected.

Routing is created between pad 1 and pad 3 and from pad 2 and pad 3. This routing does not match the From-To configuration because there is an additional pad 3 at the path between pad 1 and pad 2, so a violation of the Routing Topology rule for the From-To between pads 1 and 2 is detected.

Violations will not be detected for nets with a large number of pads (more than 20) or primitives (more than 1024).

This feature is in Open Beta and available when the PCB.Rules.CheckRoutingTopology option is enabled in the Advanced Settings dialog.

For more information, refer to the Understanding Connectivity on Your PCB page.

PCB CoDesign Improvements

Display of Primitive Names in Conflicts

When a conflict between primitives of a group object is detected, names of these primitives are now included in the list of conflicts in the PCB CoDesign panel. In the image shown below, names of primitives within a group object in conflict (pads of a component) are shown before the properties of the primitives.

For more information, refer to the PCB CoDesign page.

Merging Object Properties

When the same object properties are changed from both sides and there are no conflicts in property values, these changes no longer create a conflict and can be merged, significantly reducing the number of object conflicts.

Javascript ID: PCBCoDesigner_MergeProperties_AD24_10

A PCB area and properties of component J4 in the base version of the PCB document are shown here.

In the remote version of the PCB, 3D body opacity and pad numbers of J4 have been updated.

In the local working copy of the PCB, pad numbers of J4 have been updated in the same way as in the remote version.

After performing a comparison using the PCB CoDesigner panel, there is no conflict caused by changes in J4. These changes can be merged into the local copy of the PCB.

For more information, refer to the PCB CoDesign page.

Constraint Manager Improvements

Ability to Migrate to the Constraint Manager (Open Beta)

Included with this release is the ability to perform a one-time, one-way migration from using the PCB Rules and Constraints Editor dialog to using the Constraint Manager.

Use the Design » Migrate Project to Constraint Manager Flow command from the main menus in the PCB and schematic editors. The Migration Required dialog opens to warn that the migration will take place and it cannot be undone after the  button is clicked. Both PCB design rules and schematic directives will be transferred into applicable corresponding constraints within the Constraint Manager. Once the migration has successfully concluded, the Constraint Manager will be opened (in the context of which editor was active when you performed the migration).

If a design rule with a default scope does not exist in the PCB Rules and Constraints Editor dialog (e.g., there is no Width rule with the scope All), it will be created in the Constraint Manager as part of the migration process.

This feature is in Open Beta and available when the ConstraintManager.ProjectMigrationWizard option is enabled in the Advanced Settings dialog.

For more information, refer to the Defining Design Requirements Using the Constraint Manager page.

Improvements to Directives

Add, Update, and Remove Constraints to Imported Directives

For an already-imported directive, it is now possible to add, update and remove constraints for it using the Properties panel.

To apply changes to the data in the Constraint Manager, click the  button at the top-right of the Constraint Manager when it is accessed from the schematic side.

For more information, refer to the Defining Design Requirements Using the Constraint Manager page.

Warning about Discrepancy in ECO

When preparing the ECO to pass changes from the schematic to the PCB, a warning is now presented if there are directives that exist on the schematics that were not previously imported.

For more information, refer to the Defining Design Requirements Using the Constraint Manager page.

Harness Design Improvement

Auto-group Wires

For the Bulkhead Connector (the connector with the largest number of cavities), automatic grouping is applied to the wiring list in a harness manufacturing document (*.HarDwf), ensuring that all of its cavities are correctly grouped in the From column.

Javascript ID: HD_AutoGroupWires_AD24_10

In this design, component MAIN CONTROLLER is considered the Bulkhead Connector as it has the largest number of cavities.

In the manufacturing drawing, all cavities of MAIN CONTROLLER are grouped in the From column.

Platform Improvement

View Only Mode for Harness and Multi-board Designs (Open Beta)

A view only mode has been introduced for Harness and Multi-board projects and their associated documents. This allows you to now see and explore features that were perhaps not accessible to you previously and collaborate with colleagues working on these types of projects.

When in view only mode, no updates to projects and documents are allowed/accessible. When a project has been opened in view only mode, the Projects panel will display View Only, as shown below.

Javascript ID: MB_ViewOnly_AD24_8

An example of view only mode for a Multi-board project. The project is labeled as View Only in the Open Project dialog and the Projects panel.

When a source document of a project is opened (as shown here for a Multi-board schematic document), it is also labeled as View Only, and the document cannot be modified.

While you cannot modify anything, you can generate outputs, such as PDFs, of source documents and defined outputs from associated OutJobs.

This feature is in Open Beta and available when the System.ViewOnlyMode.Support option is enabled in the Advanced Settings dialog.

For more information, refer to the Designing with Multiple PCBs and Harness Design pages.

Data Management Improvements

Requirements Management (Open Beta)

For PCB design projects stored in a connected Altium 365 Workspace, this release delivers the ability to work with system requirements defined through the Requirements and Systems Portal. The latter is an advanced engineering management application used to ensure specification and performance compliance during system design development.

When enabled for your Altium 365 Workspace, the Requirements and Systems Portal integrates with your PCB design projects through the exchange of design data and formalized Requirement instances. The system requirements, as created in the Requirements and Systems Portal, can be placed as active instances on your design documents, referenced as tasks, and ultimately marked as verified to confirm requirement compliance.

In Altium Designer, the requirements are managed through the Requirements panel. Placed requirements are available in real-time to collaborating users – those that have shared access to the document – and are saved to the Workspace independently of the project without altering its constituent documents in any way.

This feature is in Open Beta and available when the EDMS.Requirements option is enabled in the Advanced Settings dialog.

For more information, refer to the Working with Requirements page.

Ability to Change Project Parameters from a Local Template

When creating a new project using the Create Project dialog (File » New » Project), you can now change (names and/or values) or remove parameters sourced from the selected local project template.

For more information, refer to the Creating Projects and Documents page.

SI Analyzer by Keysight (Open Beta)

More and more modern electronic devices incorporate high-speed PCB designs, and signal speeds grow as the technologies evolve (17 GHz in DDR6, 400 Gbps in QSFP++, etc.). Ensuring signal integrity (SI) is a crucial step in the high-speed design. Failure to meet the requirements of the interface developer is very likely to cause problems in further design stages, manufacturing, and performance.

To provide PCB designers with a tool for signal integrity analysis, a new solution is now available – SI Analyzer by Keysight. Provided as a software extension and available right in the Altium Designer environment, the SI Analyzer by Keysight allows performing a range of SI post-layout checks to cover the most important high-speed design parameters:

  • Impedance

  • Delay

  • Insertion Losses (IL)

  • Return Losses (RL)

This feature is in Open Beta and available when the SI Analyzer by Keysight extension is installed. Creating a new analysis document, adding/configuring nets for an analysis, as well as the review of existing SI analysis results and generation of an SI analysis report, can all be performed by anyone with a valid Altium Designer license. Performing a new SI analysis requires a valid Signal Analyzer by Keysight license. If no Signal Analyzer by Keysight license is available when running a new SI analisys, you can request a 14-day free trial using the dialog that opens.

For more information, refer to the SI Analyzer by Keysight page.

Features Made Fully Public in Altium Designer 24.10

The following features are now officially Public with this release:

Altium Designer 24.9

Released: 11 September 2024 – Version 24.9.1 (build 31)

Release Notes for Altium Designer

Altium Designer 24.8

Released: 21 August 2024 – Version 24.8.2 (build 39)

Release Notes for Altium Designer

Altium Designer 24.7

Released: 23 July 2024 – Version 24.7.2 (build 38)

Release Notes for Altium Designer

Altium Designer 24.6

Released: 18 June 2024 – Version 24.6.1 (build 21)

Release Notes for Altium Designer

Altium Designer 24.5

Released: 22 May 2024 – Version 24.5.2 (build 23) HotFix 1

Release Notes for Altium Designer

Altium Designer 24.4

Released: 16 April 2024 – Version 24.4.1 (build 13)

Release Notes for Altium Designer

Altium Designer 24.3

Released: 19 March 2024 – Version 24.3.1 (build 35)

Release Notes for Altium Designer

Altium Designer 24.2

Released: 15 February 2024 – Version 24.2.2 (build 26)

Release Notes for Altium Designer

Altium Designer 24.1

Released: 16 January 2024 – Version 24.1.2 (build 44)

Release Notes for Altium Designer 

Altium Designer 24.0

Released: 13 December 2023 – Version 24.0.1 (build 36) 

Release Notes for Altium Designer

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Note

The features available depend on your Altium product access level. Compare features included in the various levels of Altium Designer Software Subscription and functionality delivered through applications provided by the Altium 365 platform.

If you don’t see a discussed feature in your software, contact Altium Sales to find out more.

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