Setting Up the Design Constraints

Main page: Defining Design Requirements Using the Constraint Manager

Do I have the Constraint Manager?

Altium Designer suggests two distinct approaches to defining design constraints: the PCB Rule and Constraints Editor dialog and the Constraint Manager. The Constraint Manager is available in a PCB design project only if the Constraint Management option was enabled in the Create Project dialog when this project was created.

Note that this page applies only if the Constraint Manager was enabled for the tutorial project and, therefore, is available for it. To quickly check if the Constraint Manager is available for the tutorial project, open the Design main menu from the Schematic editor when the project's schematic document is open and check for the Constraint Manager command. If the Constraint Manager is not available, skip this tutorial page and go to the next page: Creating and Configuring the PCB Document.

Altium Designer's PCB editor is a rules-driven environment, meaning that as you perform actions that change the design, such as placing tracks, moving components, or autorouting the board, the software monitors each action and checks to see if the design still complies with the design constraints. If it does not, then the error is immediately highlighted as a violation. Setting up the design constraints before you start working on the board allows you to remain focused on the task of designing, confident in the knowledge that any design errors will immediately be flagged for your attention.

Design constraints are configured in the Constraint Manager (Design » Constraint Manager) accessible from both the schematic and PCB sides of the design. In this tutorial, the design constraints will be defined from the schematic side and then transferred to the PCB, along with other design data (components and nets).

All design requirements are configured as constraints in the Constraint Manager.
All design requirements are configured as constraints in the Constraint Manager.

Defining the Clearance Constraint

The first step is to define how close electrical objects that belong to different nets can be to each other.

This requirement is handled by the clearance design constraints. The Constraint Manager includes the Clearances view that presents the clearance matrix where clearances between net classes in the design can be defined. For the tutorial, a clearance of 0.25mm between all objects is suitable.

Note that entering a value into a cell in the clearance matrix or into the Clearance field will automatically apply that value to all of the fields in the grid region at the bottom of the Constraint Manager when a cell in the clearance matrix is selected. You only need to edit in the grid region when you need to define a clearance based on the object type.

Defining the Width Constraints

The width of the routing is controlled by the applicable width design constraint, which is automatically selected when you run the Interactive Routing command and click on a net.

When you are configuring the constraints, the basic approach is to set the generic constraint to target the largest number of nets and then add specific constraints to target nets with special width requirements, such as power nets. Constraint priority applies automatically based on the natural hierarchy of design objects.

For example, the tutorial design includes a number of signal nets and two power nets. The net constraint for all nets can be configured at 0.25mm. Even though the All Nets scope also targets the power nets, these nets can be specifically targeted by adding a specific constraint.

  • The width design constraint includes Min, Max, and Preferred settings. Use these if you prefer to have some flexibility during routing, for example, when you need to neck a route down in a tight area of the board. This can be done on the fly as you route by pressing 3 to cycle through the routing widths. There are also other techniques for editing the routing width; these are discussed more in the routing section.
  • Avoid using the Min and Max settings to define a single constraint to suit all sizes required in the entire design. Doing this means you forgo the ability to get Altium Designer to monitor that each design object is appropriately sized for its task.

Defining the Via Style Constraint

As you route and change layers, a via is automatically added. In this situation, the via properties are defined by the applicable via style design constraint. If you place a via from the Place menu, its values are defined by the default primitive settings. For the tutorial, you will configure the via style design constraint.

Defining the constraints is now complete. It's time to create the PCB!
If you find an issue, select the text/image and pressCtrl + Enterto send us your feedback.
Note

The features available depend on your Altium product access level. If you don’t see a discussed feature in your software, contact Altium Sales to find out more.

Content