Altium NEXUS Documentation

DoViaStitching

Modified by Susan Riege on Jul 13, 2018

Parent page: PCB Commands

The following pre-packaged resources, derived from this base command, are available:


Applied Parameters: Mode=Flood

Summary

This command is used to connect regions of copper on different layers with a pattern of stitching vias. Via Stitching is a technique used to tie together larger copper areas on different layers, in effect creating a strong vertical connection through the board structure, helping maintain a low impedance and short return loops. In RF designs stitching is used in combination with guard rings to create a via wall, helping create an electromagnetically 'quiet' PCB. Via stitching can also be used to tie areas of copper that might otherwise be isolated from their net, to that net.

Access

This command is accessed from the PCB Editor by choosing the Tools » Via Stitching/Shielding » Add Stitching to Net command from the main menus.

Use

After launching the command, the Add Stitching to Net dialog will open. Use this dialog to configure stitching settings for the design, including stitching parameters and via style. Via stitching is run as a post-process, filling free areas of copper with stitching vias. For via stitching to occur, there must be overlapping regions of copper that are attached to the specified net on different layers. Supported regions of copper include Fills, Polygons and Power Planes.

Using the selected net, the stitching algorithm identifies all Fills, Polygons and Power Planes attached to that net and attempts to connect them through the board using the specified via and stitching pattern. The via stitching algorithm treats Polygons, Fills and Planes in the following ways:

  1. Polygons and Fills that are on the same net are stitched wherever they overlap on different layers. If there are Polygons or Fills on other nets that are overlapping within that area (on another layer), stitching is not applied in that region. Overlapping Plane regions on other nets are passed through.
  2. Overlapping Plane regions on the target net are always stitched, regardless of the presence of Plane regions (on another layer) attached to other nets. Rule 1 above applies if there are Polygons or Fills overlapping in the same region.

Tips

  1. Once stitching is complete, you will need to re-pour the polygons if the applicable Polygon Connect Style design rule specifies a relief connection style.
  2. Each set of stitching vias are added to a union. A set can be removed by running the Tools » Via Stitching/Shielding » Remove Via Stitching Group command then clicking on any stitching via in the group.


Applied Parameters: Mode=Remove

Summary

This command is used to remove an existing set (or group) of stitching vias associated with a particular net in the design. Via Stitching is a technique used to tie together larger copper areas on different layers, in effect creating a strong vertical connection through the board structure, helping maintain a low impedance and short return loops. In RF designs stitching is used in combination with guard rings to create a via wall, helping create an electromagnetically 'quiet' PCB. Via stitching can also be used to tie areas of copper that might otherwise be isolated from their net to that net.

Access

This command is accessed from the PCB Editor by choosing the Tools » Via Stitching/Shielding » Remove Via Stitching Group command from the main menus.

Use

After launching the command, the cursor will change to a cross-hair and you will be prompted to choose a stitching via. Position the cursor over a via that is part of the set of stitching vias you wish to remove from the board then click or press Enter. The entire set of stitching vias (which is actually a union) will be removed.

Tips

  1. To add via stitching for a particular net in the design, run the Tools » Via Stitching/Shielding » Add Stitching to Net command from the main menus then configure stitching scope and options in the subsequent Add Stitching to Net dialog.

 

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