The Error Reporting tab of the Project Options dialog for Multi-board project (back image) and a PCB project (front image)
This tab of the Project Optionsdialog enables you to define the reporting levels for each of the possible electrical and drafting violations that can exist on source schematic documents when compiling the project. When the project is compiled, these violation settings will be used in conjunction with the settings on the Connection Matrix tab to test the source documents for violations.
Any violations that are found that have a report level of Warning, Error or Fatal Error will be displayed as violation messages in the Messages panel. In addition, if compiler errors and warnings are enabled for display on the schematic (enabled on the Schematic - Compiler page of the Preferences dialog), an offending object will display a colored squiggle beneath it.
The process of compiling is integral to producing a valid netlist for a project. In fact, it is the process of compilation that yields the unified data model of a design. Carefully check and resolve all reported errors prior to netlist generation.
When working with an Integrated Library project (*.LibPkg), the Error Reporting tab is part of the Options for Integrated Library dialog - a variation of the dialog described here. Only those violation types pertinent to compilation of this project type will be listed.
For a comprehensive reference describing each of the possible electrical and drafting violations that can exist on source documents when compiling a project, refer to the Project Compiler Violations Reference.
This is one of multiple tabs available when configuring the options for a project accessed from within the Project Options dialog. To access this dialog:
Click Project» Project Options in the Schematic or PCB Editor.
Right-click on the Project entry on the Projects panel then click Project Options from the context menu.
Only the second method of access can be used for an Integrated Library project.
This list presents all possible electrical and drafting violations that can exist on the source documents of the project. Violations themselves are gathered into the following categories:
There may be points in the design that you know will be flagged as electrical violations that you do not want to be flagged. To suppress these, place a No ERC schematic design directive object at each point.
Generally, it is better to first compile the design and examine the warnings with the default settings. For those warnings that are not an issue for the current design, the reporting level can be changed.
One option of interest is Nets with only one pin. This can be used to detect single node nets where a pin has been connected to a Port for example, but does not connect to another pin. This is set to Error by default and can be changed to No Report if the single node net is intentional.