Altium Designer's PCB Editor uses the concept of Design Rules to define the requirements of a design. These rules collectively form an 'instruction set' for the PCB Editor to follow. They cover every aspect of the design - from routing widths, clearances, plane connection styles, routing via styles, and so on - and many of the rules can be monitored in real-time by the online Design Rule Checker (DRC).
Design rules target specific objects and are applied in a hierarchical fashion. Multiple rules of the same type can be set up. It may arise that a design object is covered by more than one rule with the same scope. In this instance, a contention exists. All contentions are resolved by a priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope(s) match the object(s) being checked.
With a well-defined set of design rules, you can successfully complete board designs with varying and often stringent design requirements. And as the PCB Editor is rules-driven, taking the time to set up the rules at the outset of the design will enable you to effectively get on with the job of designing, safe in the knowledge that the rules system is working hard to ensure that success.
Define your rules in the PCB Rules And Constraints Editor dialog, accessed from the PCB editor by choosing the Design » Rules command from the main menus.
For a high-level view of working with the design rules system, see Defining, Scoping & Managing PCB Design Rules. For an overview of the system used to verify adherence to defined rules, see Design Rule Checking.
The Design Rules are divided into separate categories to make it easier to locate and configure your desired rule(s). The categories and their specific rules are described below.
This rule defines the minimum clearance allowed between any two primitive objects on a copper layer. Either a single value for clearance can be specified, or different clearances for different object pairings, through use of a dedicated Minimum Clearance Matrix. The latter, in combination with rule-scoping, provides the flexibility to build a concise and targeted set of clearance rules to meet even the most stringent of clearance needs.
Default constraints for the Clearance rule. Roll the mouse over the image to compare the two modes available.
The rule scope returns a set of objects, the constraints detailed below are then applied to that set of objects:
Different Nets Only
Same Net Only
► Learn more about Differential Pair Clearance Checking
For a defined Same-Net Only Clearance rule, the general approach is that if two objects are touching (i.e. connected), then they are not deemed to be in violation of the rule. The exception to this is when checking the clearance between via and SMD pad objects in the same net. When a via and SMD pad have soldermask clearance, and the two are too close together, the soldermask bridge between the two objects can disappear, and solder paste will flow down into the via during the soldering process, creating a bad solder joint on the SMD pad. Even if a via and SMD pad are connected with a trace or overlapping, they are deemed to be in violation when the distance between them is less than the Via-SMD Pad clearance in the Same-Net Clearance rule.
Configure the minimum distance allowed between a via and SMD pad by setting the Via-SMD Pad clearance in the Same-Net Clearance rule. If the via and SMD pad must touch or overlap, you must define a suitable Via Under SMD design rule (High Speed category) and enable the Allow Vias under SMD Pads constraint.
For many users, there is no great difference between Track and Arc primitives. And when it comes to Fill, Region, and Polygon objects, most users just see these as more 'copper.' With this in mind, the minimum clearance matrix for the Clearance rule has been enhanced to operate in two modes:
Definition of clearance values in the matrix can be performed in the following ways:
With the required selection made (either a single cell or multiple cells), making a change to the current value is simply a case of typing the new value required. To submit the newly entered value, either click away on another cell, or press Enter. All cells in the selection will be updated with the new value.
Example multi-cell editing. Notice that as different values for clearance now exist for one or more object pairings, the Minimum Clearance constraint has changed to N/A, to reflect that a single clearance value is no longer being applied for all object-to-object clearance combinations.
Designers can check clearances between the edges of drill holes and neighboring copper objects on signal layers. This is particularly beneficial in preventing the routing of track too near to a drilled hole, which could otherwise suffer from any potential wandering of the drill during board fabrication. The row at the bottom of the Clearance rule's minimum clearance matrix is used to define the desired clearances.
Set clearance values to catch any copper objects that are too close to the edges of drill holes in the design.
Designers can also check clearances between split plane regions on internal plane layers. How clearance is defined depends on the mode in which you are using the minimum clearance matrix:
A violation will appear in the form:
Clearance Constraint: (<CurrentClearance> < <DefinedClearance>) Between Split Plane (<NetName>) on <InternalPlaneLayerName> And Split Plane (<NetName>) on <InternalPlaneLayerName>,
Clearance Constraint: (32.36mil < 34mil) Between Split Plane (GND) on Internal Plane 1 And Split Plane (NetC6) on Internal Plane 1
Clearance checking between split plane regions on an internal layer. In this case, the clearance value of 34mil has been entered in the Region-Region cell, as clearances are being defined using the Advanced mode of the matrix.
Differential pairs present unique design challenges, often requiring a specific within-pair clearance as well as a pair-to-pair clearance, and potentially a third rule to control the pair-to-all other nets, clearance. To support this, the Constraints region includes the dropdown where you can choose Same Differential Pair and Different Differential Pair options.
pair-to-all other nets
Same Differential Pair
Different Differential Pair
For example, if the nets within the differential pairs require a tighter clearance than the general board clearance, this can be achieved by using the Same Differential Pair constraint option, as shown below. Note that even though the rule scope applies to All net objects in the design, the Constraint setting restricts it to only apply to objects in the Same Differential Pair.
This result could also be achieved by scoping the rule to only apply to differential pair objects (eg, InAnyDifferentialPair), as shown below. Note that this rule would also apply between a net in a differential pair to any other net object in the design, so this approach should only be used if you have other higher priority rule(s) that define the DiffPairNet-to-DiffPairNet and/or DiffPairNet-to-Any requirements. If this approach is used, the Priority of the differential pair rules must also be configured correctly, with the rule with a tighter clearance requirement having a higher priority.
A similar approach can be used to control the clearance between differential pairs. The image below shows how the Different Differential Pair constraint can be used to achieve this.
As with the previous example, it could also be achieved using the rule scope, instead of the Different Differential Pairs constraint. Remember that the rule priorities must be configured so the rule with the tighter clearance requirement has a higher priority.
Different Differential Pairs
To define a different clearance from a differential pair net to any other net object, the following rule could be used.
This could be further refined so that it only applies between differential pair objects and non-differential pair objects, as shown below.
► Learn more about scoping Differential Pair design rules
► Learn more about Differential Pair Routing
Online DRC, Batch DRC, interactive routing, autorouting, and during polygon placement.
This rule tests for short circuits between primitive objects on the copper (signal and plane) layers. A short circuit exists when two objects that have different net names touch.
Default constraints for the Short-Circuit rule
Allow Short Circuit - defines whether the target nets falling under the two scopes (full queries) of the rule can be short-circuited or not. If you require two different nets to be shorted together, for example when connecting two ground systems within a design, ensure that this option is enabled.
Online DRC, Batch DRC, and during autorouting.
In a Printed Electronics design when different nets cross over on different layers, they are flagged as a short circuit. These cross-overs are isolated by placing a dielectric patch on a non-conductive layer.
This rule tests the completion status of each net that falls under the scope (full query) of the rule. If a net is incomplete then each completed section (sub-net) is listed along with the routing completion. The routing completion is defined as:
(connections complete / total number of connections) x 100
The PCB Editor's Design Rule Checking system typically sees a net as being routed if all nodes in that net (component pads) are connected through the use of net-aware design objects (tracks, arcs, pads, vias, and polygons). These objects are considered connected if they touch each other. However, while simply touching makes a perceived connection to the software, when it comes time to fabricate the board, the fragility of some of these 'connections' can cause critical issues, especially where the objects - for example two contiguous track segments, or a track entering a pad/via - are only slightly touching. Such connections are often referred to as 'Bad Connections', 'Poor Connections', or 'Incomplete Connections'. This rule can also be configured to test for such poor connections.
Default constraints for the Un-Routed Net rule
Check for incomplete connections - with this option enabled, the following additional checks on connectivity between applicable design objects are made:
Copper layer objects scoped by an Un-Routed Net rule and with no net assigned will be reported as dead copper during Batch DRC when the Report Dead Copper larger than option is enabled in the Design Rule Checker dialog and the Un-Routed Net rule type is enabled for Batch DRC in this dialog. Also, copper layer objects with a net assignment but not connected to any pad of the same net and not connected with other objects of the same net with connection lines will be reported as dead copper.
Detection of dead copper primitives with no net assigned is available by setting the value of the PCB.Rules.DeadCopperNoNet option in the Advanced Settings dialog. The default value is 2.
0 - Do not check any.
1 - Check all.
2 - Check all except free Pads, Text objects, and objects in Components.
Default Rule: not required
This rule detects pins that have no net assigned and no connecting tracks.
Online DRC and Batch DRC.
This rule detects polygons that are still shelved and/or have been modified but have not yet been repoured.
Default constraints for the Modified Polygon rule
This rule tests the creepage distance between the targeted signals across the board surface through unplated holes, cutouts, and around the board edge.
Default constraints for the Creepage distance rule
This rule defines the width of tracks placed on the copper (signal) layers.
Constraints for the Width rule, which apply to all layers. Enter layer-specific values in the grid (hover the cursor over to show).
Use Impedance Profile - this option becomes available when there is at least one impedance profile defined in the Layer Stack Manager. When enabled, use the drop-down to select the impedance profile desired. When the rule is configured in this mode, the Preferred Width required on each routing layer is calculated as part of the specified impedance profile. Once the rule is defined, as you route a net that falls under the scope of the rule, the track width will automatically be set to the width required to meet the specified impedance for that layer. When this option is enabled the Preferred Width cannot be edited in the rule, but the Min Width and Max Width values can.
► Learn more about Configuring the Layer Stack for Controlled Impedance Routing
Show values for layer stack - this option appears in the dialog when there are multiple layer stacks defined in the Layer Stack Manager. If the board includes multiple layer stacks then the Width Constraints must be configured for each of the layer stacks, using either the all-layer fields above the image or the layer-specific fields in the Layer Attributes Table.
► Learn more about Defining and Configuring Substacks
Configure the Constraints for each layer stack in the design.
When defining values for the minimum, maximum and preferred routing widths, the Layer Attributes Table will highlight any invalid entries by using red text. This could happen, for example, when you specify a minimum constraint value that is greater than the maximum constraint value. The incorrect rule definition is further highlighted by the rule name becoming red in both the folder-tree pane and the respective summary lists, in the PCB Rules and Constraints Editor dialog.
The Preferred Width setting is obeyed by the Autorouter.
The Min Width and Max Width settings are obeyed by the Online DRC and Batch DRC. They also determine the range of permissible values that can be used during interactive routing (press Tab key while routing to change the trace width within the defined range, through the Properties panel). If a value is entered outside of this range, it will automatically be clipped.
The width of each net in a differential pair is monitored by the applicable Differential Pairs Routing rule.
This rule specifies the topology to be employed when routing nets on the board. The topology of a net is the arrangement or pattern of the pin-to-pin connections. By default, pin-to-pin connections of each net are arranged to give the shortest overall connection length. A topology is applied to a net for a variety of reasons; for high speed designs where signal reflections must be minimized the net is arranged with a daisy chain topology; for ground nets a star topology could be applied to ensure that all tracks come back to a common point.
Default constraint for the Routing Topology rule
Topology - defines the topology to be used for the net(s) targeted by the scope (full query) of the rule. The following topologies can be applied:
When using the Autorouter, routing completion time may be longer when using topologies other than Shortest.
This rule assigns a routing priority to the net(s) targeted by the rule. The Autorouter uses the assigned priority value to gauge the routing importance of each net in the design and hence determine which nets should be routed first.
Default constraint for the Routing Priority rule
Routing Priority - the priority value assigned to the net(s) targeted by the scope (full query) of the rule. Enter a value between 0 and 100, whereby the higher the number assigned, the greater the priority when routing.
This rule specifies which layers are allowed to be used for routing.
Default constraints for the Routing Layers rule
Enabled Layers - each of the signal layers currently defined for the design, as defined by the layer stackup, are listed. Use the associated Allow Routing option to enable/disable routing on a layer, as required.
Online DRC, Batch DRC, during interactive routing, and while autorouting.
When using the Autorouter, the routing direction for each enabled signal layer in the design is defined as part of the Situs Autorouter setup. Directions are specified in the Layer Directions dialog, accessed by clicking the Edit Layer Directions button in the Situs Routing Strategies dialog.
This rule specifies the corner style to be used during autorouting.
Default constraints for the Routing Corners rule
This rule is intended for use by third party Autorouters that implement 45° routing as a post process. It is not followed by the Situs Autorouter, which implements 45° routing as a native process.
This rule specifies the style of vias that can be used when routing. You have the option to define specific Min/Max/Preferred values for the via's diameter and hole size - defined as part of the rule's constraints - or use via templates available to the board design.
Default constraints for the Routing Via Style rule. Roll the mouse over the image to compare the two modes available.
Mode - use the drop-down to choose from the following two modes:
When this mode is chosen, the constraints region changes to present the following options:
Online DRC, Batch DRC, during autorouting, during interactive routing.
When the mode of the rule is set to Min/Max preferred, the following considerations apply:
User Choice means the last-used via settings, or template chosen. To change the current User Choice values, press Shift+V during interactive routing when there is a via floating on the cursor. The Choose Via Sizes dialog will open, select a Via Template or enter the required values (within the Min/Max rule range).
When the mode of the rule is set to Template preferred, the following considerations apply:
In order to control the size of blind and buried vias, individual rules can be set up targeting the different layer pairs. For example, to control the via size for blind vias between the top layer and mid layer 1, the following scope (Full Query) can be used:
(StartLayer = 'Top Layer') and (StopLayer = 'Mid-Layer1')
To control the via size for buried vias between mid layer 2 and mid layer 3, the following scope would be used:
(StartLayer = 'Mid-Layer2') and (StopLayer = 'Mid-Layer3')
Alternatively, instead of creating individual rules, you can expand the one rule query using ORs as follows:
((StartLayer = 'Top Layer') and (StopLayer = 'Mid-Layer1')) or((StartLayer = ' Mid-Layer2') and (StopLayer = 'Mid-Layer3'))
This rule specifies fanout options to be used when fanning out the pads of surface mount components in the design that connect to signal and/or power plane nets. Fanout essentially turns an SMT pad into a thru-hole pad, from a routing point of view, by adding a via and connecting track. This greatly increases the probability of successfully routing the board, as a signal is made available to all routing layers instead of just the top or bottom layer. This is particularly needed in high-density designs where routing space is very tight.
Default constraints for the Fanout Control rule (Fanout_Default)
In Then Out
Out Then In
Alternating In and Out
Away From Center
Close To Pad (Follow Rules)
Centered Between Pads
During interactive routing and autorouting.
(CompPinCount < 5)
This rule defines the routing width of each net in a differential pair, and the clearance (or gap) between the nets in that pair. Differential pairs are typically routed with specific width-gap settings to deliver the required differential impedance needed for that net-pair.
► Learn more about Controlled Impedance Routing
Default constraints for the Differential Pairs Routing rule
Online DRC, Batch DRC, interactive routing (and re-routing), autorouting, interactive length tuning (Min Gap is applied), and when interactively modifying the pair, such as sliding a track segment of one of the nets in the pair.
This rule specifies the minimum distance from the edge of a surface mount pad to the first routing corner.
Default constraints for the SMD To Corner rule
Distance - the value for the minimum permissible distance from the SMD pad edge to the start of the first routing corner.
Online DRC and Batch DRC, and Interactive Routing.
The interactive router will obey this rule by maintaining a straight pad exit trace emanating from the pad center on any allowed "entry angle" (see SMD Entry rule), at least to the distance specified.
The SMD to Corner rule defines the distance to the first corner. Use the SMD Entry rule to specify where the route is allowed to enter (or exit) the SMD pad.
This rule specifies the maximum routing length from the center of a surface mount pad to the center of the pad/via connecting to a power plane.
Default constraints for the SMD To Plane rule
Distance - the value for the maximum permissible distance from SMD pad to pad/via connecting to the power plane.
This rule specifies the maximum ratio of the track width to the SMD pad width, expressed as a percentage.
Default constraints for the SMD Neck-Down rule
Neck-Down - the percentage value for the maximum permissible ratio of track width to SMD pad width. Entering a larger value will allow for the use of greater width track.
This rule specifies the direction(s) a track can enter, or exit, an SMD pad.
Default constraints for the SMD Entry rule
Side length > 2x End length
2mm x 1mm
2.1mm x 1mm
Online DRC, Batch DRC, and Interactive Routing.
The rule works in harmony with the SMD To Corner design rule, configure both to ensure neat SMD routing.
The SMD Entry rule specifies where the route is allowed to enter/exit the SMD pad, all rule checkboxes are cleared in this example animation. Use the SMD to Corner rule to define the distance to the first corner.
The shape that is created on the solder mask layer at each pad and via site is the pad or via shape (or hole), expanded or contracted radially by the amount specified by this rule.
Default constraints for the Solder Mask Expansion rule
Expansion bottom - this constraint is used to specify the value applied to the initial pad/via shape (or hole) to obtain the final shape on the bottom solder mask layer.
Solder Mask From The Hole Edge - use this constraint to determine the reference for the calculated mask expansion. When disabled, the perimeter of the object is used (the copper land edge for a pad or via). When enabled, the perimeter of the pad/via hole is used. For example, a 5mil Solder Mask Expansion applied to a 60mil diameter round pad will create a mask opening of 70mil (pad diameter + (2 x expansion)). If the reference is the hole edge, and the same pad had a hole diameter of 30mil, then the 70mil mask opening would be achieved by a 20mil expansion (hole diameter + (2 x expansion)).
pad diameter + (2 x expansion)
hole diameter + (2 x expansion)
During output generation.
The shape that is created on the paste mask layer at each pad site is the pad shape, expanded or contracted radially by the amount specified by this rule.
Default constraints for the Paste Mask Expansion rule
This rule specifies the style of the connection from a component pin to a power plane.
Default constraints for the Power Plane Connect Style rule. Roll the mouse over the image to compare the two modes of operation available.
The following constraints apply only when using the Relief Connect style:
This rule specifies the radial clearance created around vias and pads that pass through but are not connected to a power plane.
Default constraints for the Power Plane Clearance Rule
Clearance - the value for the radial clearance.
This rule specifies the style of the connection from a component pad, or routed via, to a polygon plane.
Default constraints for the Polygon Connect Style rule. Roll the mouse over the image to compare the two modes of operation available.
During polygon pour.
The Fabrication Testpoint Style and Assembly Testpoint Style design rules specify the allowable physical parameters of pads and vias that are to be considered for use as testpoints for bare-board fabrication testing, or in-circuit assembly testing respectively. The constraints between these two rules are identical.
Default constraints for the Fabrication and Assembly Testpoint Style rule
The following options allow you to specify pad/via diameter and hole size criteria when testing for valid testpoints:
The following options allow you to define clearance constraints specific to board testing:
Distance to Via Hole Centers - specifies the minimum permissable distance from the center of a testpoint, to the center of an adjacent via (the center of the via's hole).
Use of a grid is most appropriate when targeting a non-custom bed-of-nails fixture. To include use of a grid, enable the Use Grid option. To disable use of a grid, enable the No Grid option.
If you do want to use a grid, the following options allow you to define it in a more comprehensive manner:
Use these options to specify on which side of the board prospective testpoint pad/via locations can reside - either Top, Bottom, or both.
Use this option to enable the use of pads/vias located underneath components (on the same side of the board as the components) for testpoint purposes. This option would typically be enabled in a Fabrication Testpoint Style rule, but not for an Assembly Testpoint Style rule - as the pad/via will typically not be accessible once the board is populated with components.
Use this region of the constraints to determine which objects the rule is to apply to. Simply enable the checkbox for the objects to be included - SMD Pads, Vias, Thru-hole Pads - and click on the Set Scope button. The logical query for the rule scope will be created and entered into the Full Query region for the rule.
This rule is obeyed by the Testpoint Manager, the Autorouter, the Online and Batch DRC, and during output generation. The Online DRC and Batch DRC test all attributes of the rule except the Preferred Size and Preferred Hole Size - these settings are used by the Autorouter to define the size of testpoint pads/vias that the Autorouter places.
The Fabrication Testpoint Usage and Assembly Testpoint Usage design rules specify which nets require testpoints for bare-board fabrication testing, or in-circuit assembly testing, respectively. The constraints between these two rules are identical.
Default constraints for the Fabrication and Assembly Testpoint Usage rule
This rule is obeyed by the Testpoint Manager, Autorouter, the Online and Batch DRC, and during output generation.
This rule specifies the minimum annular ring required for a pad or via. The annular ring is measured radially, from the edge of the pad/via hole to the edge of the pad/via (also referred to as the land perimeter).
Default constraints for the Minimum Annular Ring rule
Minimum Annular Ring (x-y) - the minimum value for the annular ring around the pads/vias targeted by the rule.
Violations of the Minimum Annular Ring design rule are detected for pads and vias with connections on layers on which pad/via shapes are smaller than the pad/via hole (e.g., if pad/via shapes have been configured manually in the Properties panel or removed by using the Remove Unused Pad Shapes tool).
This rule specifies the minimum angle permitted between any objects in the same net. The Acute Angle rule works on nets only. It finds all the acute angles created by any objects in one net. The rule essentially creates a contour from all the primitives in a net (on the same layer) and then analyzes this contour for any points that might create an angle smaller than the acute angle limit value.
Default constraints for the Acute Angle rule
This rule specifies the maximum and minimum hole size for pads and vias in the design. The hole size is the diameter of the hole to be drilled through the pad/via during fabrication.
Default constraints for the Hole Size rule
This rule checks to ensure that the used via types match the currently defined via types. The used via types are determined from the vias and pads found in the board. The permissible via types are defined on the Via Types tab of the Layer Stack Manager.
Default constraint for the Layer Pairs rule
Enforce layer pairs settings – specifies whether the check is made or not.
Online DRC, Batch DRC, and during interactive routing.
This rule ensures checking of manufacturing compatibility of drilled holes. When enabled, it will flag any multiple vias / pads at the same location, or overlapping pad / via holes. There is also an option to determine whether stacked micro vias are allowed or not.
Default constraints for the Hole To Hole Clearance rule
Allow Stacked Micro Vias - enable this option to allow micro vias to be stacked.
Learn more about MicroVias
This rule helps identify narrow sections of solder mask that may cause manufacturing problems at a later stage. Ensuring that there is a minimum width of solder mask across the board, this rule checks that the distance between any two solder mask openings is equal to, or greater than, a user-specified minimum value. This includes the pads, vias, and any primitives that reside on solder mask layers. It also checks Top and Bottom sides independently.
Default constraint for the Minimum Solder Mask Sliver rule
Minimum Solder Mask Sliver - specifies the minimum allowed width of solder mask.
This rule checks the clearance between any silkscreen primitive and any solder mask primitive, or exposed copper-layer primitive (exposed through openings in the solder mask). The check ensures that the distance is equal to, or greater than, the value specified in the constraint.
Many manufacturers routinely strip (or 'clip') silkscreen to the mask opening and not just to the copper pad. However, doing so can render silkscreen text unreadable. Being able to catch such occurrences, through DRC, allows you to manipulate offending silkscreen text prior to sending the board to manufacturing.
Default constraints for the Silk To Solder Mask Clearance rule
Check Clearance To Exposed Copper
This rule defines the minimum clearance allowed between text and other objects on a silkscreen layer.
Default constraint for the Silk To Silk Clearance rule
Silk Text to Any Silk Object Clearance - specifies the minimum permissible clearance between any two silkscreen objects.
This rule operates at a net level in the design to flag any open-ended track/arc primitive, or open-ended track/arc that is terminated with a via, and thus forms an antenna.
Default constraint for the Net Antennae rule
Net Antennae Tolerance - maximum permissible length for the stub of an open-ended track/arc primitive (or one that terminates in a via).
This rule defines the minimum clearance allowed from design objects that are fabricated, to edges of the board. Either a single clearance value can be specified for all object-to-edge possibilities, or different clearances for different pairings can be defined, through the use of a dedicated Minimum Clearance Matrix. The terms Board Outline and Board Edge are general names used interchangeably to describe the outer edge of the board. The term edge is defined in the table below the image. The Board Outline Clearance design rule checks object-to-edge clearances on the electrical and overlay (silkscreen) layers.
Default constraints for the Board Outline Clearance rule
With the required selection made (either a single cell or multiple cells), making a change to the current value is simply a case of typing the new value required. To submit the newly entered value, either click away on another call, or press Enter. All cells in the selection will be updated with the new value.
Online DRC, Batch DRC, interactive routing, and autorouting.
This rule specifies the distance two track segments can run in parallel, for a given separation.
Default constraints for the Parallel Segment rule
This rule detects parallel track segments that are within the parallel gap setting, then adds all segment lengths that are in those nets. When the sum of these segment lengths exceeds the parallel limit, a DRC violation is flagged. A simple example is shown below.
This rule specifies the minimum and maximum lengths of a net.
Default constraints for the Length rule
This rule specifies the allowable difference in net lengths. This rule is essential in a high-speed design, where the challenge is not just about how long it takes the signals to arrive (which is determined by their overall length), but how important it is that the specified signals arrives at the same time. Depending on the signal switching speeds, the function of the signal, and the materials used in the board, the allowed difference could be as much as 500mils, or as little as 1mil.
The set of nets being targeted is defined by the scope of the rule (as defined by its full query), with the reference length (the longest net in the set) being determined by the rule scope, in combination with the Constraints settings. Other targeted nets will pass the rule if their Current Length is:
(LongestLength - tolerance) ≤ CurrentLength ≤ LongestLength
Default constraints for the Matched Lengths rule. Roll the mouse over the image to compare the two modes of operation available.
Source Target - this drop-down is only available when an xSignal class (or all xSignals of the design) is used as the rule scope. Select an xSignal from the drop-down to use its length as a target for other xSignals scoped by the rule. When an xSignal is selected as a source target, other targeted xSignals will pass the rule if their Current Length is:
(TargetLength - tolerance) ≤ CurrentLength ≤ (TargetLength + tolerance)
Online DRC, Batch DRC, the Equalize Net Lengths feature, interactive length tuning.
Refer to the Length Tuning page to learn more about interactively tuning route lengths.
Refer to the Differential Pair Routing page to learn more about routing differential pairs.
Refer to the Defining High Speed Signal Paths with xSignals page to learn more about working with xSignals.
This rule specifies the maximum permissible stub length for a net with a daisy chain topology.
Default constraints for the Daisy Chain Stub Length rule
Maximum Stub Length - the value for the maximum stub length allowed.
This rule specifies whether vias can be placed under SMD pads.
Default constraints for the Vias Under SMD rule
Allow Vias under SMD Pads - specifies whether vias can be placed under the pads of a Surface Mount Device (SMD).
Multiple rules have been defined to only allow vias under the pads: in a class of pads, all pads in a class of components, and all pads in a specific footprint.
Multiple rules have been defined to only allow zero clearance between vias (and via holes) and SMD pads for: MicroVias using a specific PadVia Template, or IPC4761 Type 7 compliant vias.
This rule specifies the maximum number of vias permitted for each individual net in the current design.
Default constraints for the Maximum Via Count rule
Maximum Via Count - the maximum number of vias permitted in each individual net falling under the defined scope of the rule.
A stub is the length of via or pad barrel that protrudes beyond the last-used signal layer that the via/pad connects on. Back drilling will be applied to suitable vias/pads in nets targeted by this rule, in accordance with the enabled side-of-board Layer checkboxes, and the back drill pairs defined on the Back Drills tab of the Layer Stack Manager.
As well as being used to define which vias/pads are to be considered for back drilling, during design rule checking this rule tests for via and pad stubs longer than the specified Max Stub Length, for all nets targeted by this rule (regardless of whether back drilling has been applied to that via or pad). This rule also specifies how much larger the drill size must be for vias and pads that are back drilled.
Default constraints for the Max Stub Length rule
This rule specifies a continuous signal return path along the designated reference layer above or below the signals targeted. The return path can be created from fills, regions, and polygon pours placed on a signal layer or plane layers.
Default constraints for the Return Path rule
This rule can be used in the following ways:
Default constraints for the Room Definition rule
If you need a complex room shape based on precise locations, the shape can be created as an outline by placing a sequence of lines (and arcs), and then selecting and converted this outline to a room by running the Tools » Convert » Create Room from Selected Primitives command. Note that the end points of adjoining track/arc segments must coincide for this command to correctly detect the shape. Hover the cursor over the image below to see the room.
A Room can be used as a Query for another rule by referring to it by its Name, as shown above.
Note that within the room, the routing width, the plane connection style, and the solder mask expansion have different values from the values outside of the room.
This rule specifies the minimum distance that components can be placed from each other. Component clearance includes the clearance between 3D models included as part of the component footprint. In the absence of 3D models, or when the Check clearance by component boundary option is enabled in the rule constraints, each component's selection area is used instead.
The default behavior for the component selection area, is the area defined by the combined geometries on the Courtyard Layer-Type + the Silkscreen + 3D Body objects + Copper layers (strings are excluded). This is referred to as the By Graphic selection mode. If required, the component selection area can be switched from the default By Graphic mode, to the By Layer mode. In the By Layer mode, the first layer containing geometries is used, in the following order: Courtyard (Layer-Type, not Layer Name); 3D Body; Silkscreen + Copper Layers; Copper Layers. The mode is chosen by setting the value of the PCB.ComponentSelection Advanced Setting. Learn more about the component selection area and the available selection modes. Learn more about Mechanical Layers and the Courtyard Layer Type.
Component clearance is calculated using accurate 3D meshing to define the shape and contour for the component through its associated 3D model. These can be embedded true 3D models, or extruded 2D shapes. Using 3D bodies provides the greatest accuracy when it comes to clearance checking, particularly in the vertical sense and in the context of complex component shapes.
In the description above, the term 3D model means the actual shape of the included true 3D model is used. True 3D models are stored in a 3D Body object, automatically sized to the smallest rectangular prism that encloses that model. The term 3D Body refers to the rectangular prism that encloses the true 3D model, not the shape of the true 3D model that it holds.
Default constraints for the Component Clearance rule
Show actual violation distances – enable this option to show lines between the points of greatest violation between components. The distance of the line is displayed and can be useful in calculating the distance required to move an object to resolve the violation.
The rule is not currently observed by the DRC tool.
This rule specifies the layers on which components can be placed.
Default constraints for the Permitted Layers rule
Permitted Layers - the layers permitted to be used when placing components. The following layer options are available:
The rule acts as a test when performing a Batch DRC, to ensure components - targeted by the query expression of the rule's scope - are being placed only on a permitted layer. Parameters specified for components on the schematic, and that have been brought across into footprints on the PCB, can be used to great effect for this very purpose. For example, to check that components that do not support wave soldering are not placed on the bottom layer, a rule of this type can be defined. If we consider a component parameter, SupportsWaveSolder, has been defined for components and brought across as parameters of the footprints in the PCB, then the rule scope might be:
CompParameterValue('SupportsWaveSolder') <> 'Yes'
and only the Top Layer constraint would be permitted, with the Bottom Layer constraint disabled.
This rule specifies height restrictions for components placed within the design.
Default constraints for the Height rule
The Preferred setting is obeyed when displaying the board in 3D. The Minimum and Maximum settings are obeyed by the Online DRC and Batch DRC.
This rule specifies the characteristics of the stimulus signal used when performing a signal integrity analysis on the design. This is the signal that is injected at each output pin on the net under test. The worst-case result is returned during design rule checking.
Default constraints for the Signal Stimulus rule
Batch DRC and during Signal Integrity analysis.
When performing a Crosstalk analysis, an Aggressor net will be injected with the stimulus defined in the Stimulus design rule, the LOW and HIGH levels of which are dependent on the model used for the driving output pin. A Victim net will get a Constant Low level voltage injected into it, with the level again being dependent on the model used for the output pin.
This rule specifies the maximum allowable overshoot (ringing below the base value) on the falling edge of the signal.
Default constraints for the Overshoot - Falling Edge rule
Maximum (Volts) - the value for the maximum permissible overshoot on the falling edge of the signal.
This rule specifies the maximum allowable overshoot (ringing above the top value) on the rising edge of the signal.
Default constraints for the Overshoot - Rising Edge rule
Maximum (Volts) - the value for the maximum permissible overshoot on the rising edge of the signal.
This rule specifies the maximum allowable undershoot (ringing above the base value) on the falling edge of the signal.
Default constraints for the Undershoot - Falling Edge rule
Maximum (Volts) - the value for the maximum permissible undershoot on the falling edge of the signal.
This rule specifies the maximum allowable undershoot (ringing below the top value) on the rising edge of the signal.
Default constraints for the Undershoot - Rising Edge rule
Maximum (Volts) - the value for the maximum permissible undershoot on the rising edge of the signal.
This rule specifies the minimum and maximum net impedance allowed. Net impedance is a function of the conductor geometry and conductivity, the surrounding dielectric material (the board base material, multi-layer insulation, solder mask, etc) and the physical geometry of the board (distance to other conductors in the z-plane).
Default constraints for the Impedance rule
This rule specifies the minimum voltage level that a signal can settle to in the high state (the top value).
Default constraints for the Signal Top Value rule
Minimum (Volts) - the value for the minimum permissible top value voltage.
This rule specifies the maximum voltage level that a signal can settle to in the low state (the base value).
Default constraints for the Signal Base Value rule
Maximum (Volts) - the value for the maximum permissible base value voltage.
This rule specifies the maximum allowable flight time on signal rising edge. Flight time is the signal delay time introduced by the interconnect structure. It is calculated as the time it takes to drive the signal on the net to the threshold voltage (marking the transition from signal LOW to signal HIGH), less the time it would take to drive a reference load (connected directly to the output) to the threshold voltage.
Default constraints for the Flight Time - Rising Edge rule
Maximum (seconds) - the value for the maximum permissible flight time on the rising edge of the signal.
This rule specifies the maximum allowable flight time on signal falling edge. Flight time is the signal delay time introduced by the interconnect structure. It is calculated as the time it takes for the signal on the net to fall to the threshold voltage (marking the transition from signal HIGH to signal LOW), less the time it would take for a reference load (connected directly to the output) to fall to the threshold voltage.
Default constraints for the Flight Time - Falling Edge rule
Maximum (seconds) - the value for the maximum permissible flight time on the falling edge of the signal.
This rule specifies the maximum allowable slope time on the rising edge of the signal. Rising edge slope is the time it takes for a signal to rise from the threshold voltage (VT), to a valid high (VIH).
Default constraints for the Slope - Rising Edge rule
Maximum (seconds) - the value for the maximum permissible rising edge slope time.
This rule specifies the maximum allowable slope time on the falling edge of the signal. Falling edge slope is the time it takes for a signal to fall from the threshold voltage (VT), to a valid low (VIL). Constraints.
Default constraints for the Slope - Falling Edge rule
Maximum (seconds) - the value for the maximum permissible falling edge slope time.
This rule identifies a supply net and specifies its voltage (or set of nets using the net class scope).
Default constraints for the Supply Nets rule
Voltage - the voltage value for the net(s) falling under the scope (full query) of the rule.
The supply net(s) can be specified by choosing the Net or Net Class from the drop-down field in the Where The Object Matches region of the PCB Rules and Constraints Editor dialog, and then choosing the required net or net class from the corresponding secondary drop-down list. The corresponding Full Query for the rules' scope will be as follows: InNet('NetName') - for a single net; InNetClass('NetClassName') - for a net class.