Working with the Signal Top Value Design Rule on a PCB in Altium Designer
Created: 6月 05, 2015 | Updated: 9月 26, 2016
| Applies to version: 15.1
現在、バージョン 15.1. をご覧頂いています。最新情報については、バージョン Working with the Signal Top Value Design Rule on a PCB in Altium Designer の 21 をご覧ください。
Rule category: Signal Integrity
Rule classification: Unary
Summary
This rule specifies the minimum voltage level that a signal can settle to in the high state (the top value).
Constraints
Default constraints for the Signal Top Value rule.
- Minimum (Volts) - the value for the minimum permissible top value voltage.
How Duplicate Rule Contentions are Resolved
All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope expression matches the object(s) being checked.
Rule Application
Batch DRC and during Signal Integrity analysis.
