Signal Integrity Design Rule Types Available for PCB Layout in Altium Designer

The design rules of the Signal Integrity category are described below.

The Signal Integrity category of design rules.
The Signal Integrity category of design rules.


Signal Stimulus

Default Rule: not required

This rule specifies the characteristics of the stimulus signal used when performing a signal integrity analysis on the design. This is the signal that is injected at each output pin on the net under test. The worst-case result is returned during design rule checking.

Constraints

Default constraints for the Signal Stimulus rule
Default constraints for the Signal Stimulus rule

  • Stimulus Kind - specifies the type of stimulus signal that is injected during signal integrity analysis. The following stimulus types are available:
    • Constant Level - the stimulus signal remains at a constant voltage - either High or Low - depending on the chosen Start Level option
    • Single Pulse - the stimulus signal is a single pulse, whose characteristics are defined by the Start Level, Start Time and Stop Time options
    • Periodic Pulse - the stimulus signal is a continuous pulse train, whose characteristics are defined by the Start Level, Start Time, Stop Time and Period Time options.
  • Start Level - specifies the voltage level used for the Constant Level stimulus signal, or the initial voltage level for the pulse-based stimulus signals. The following levels are available:
    • Low Level - defined as the LOW level voltage for the output pin - dependent on the model used for the pin
    • High Level - defined as the HIGH level voltage for the output pin - dependent on the model used for the pin.
  • Start Time (s) - the start time for a pulse-based stimulus signal. Used in calculating the width of the pulse.
  • Stop Time (s) - the stop time for a pulse-based stimulus signal. Used in calculating the width of the pulse.
  • Period Time (s)the time between pulses in a periodic pulse train stimulus signal. After the period time has elapsed, another identical pulse of width Stop Time - Start Time is injected.
Rule Application

Batch DRC and during Signal Integrity analysis.

Note

When performing a Crosstalk analysis, an Aggressor net will be injected with the stimulus defined in the Stimulus design rule, the LOW and HIGH levels of which are dependent on the model used for the driving output pin. A Victim net will get a Constant Low level voltage injected into it, with the level again being dependent on the model used for the output pin.


Overshoot - Falling Edge

Default Rule: not required

This rule specifies the maximum allowable overshoot (ringing below the base value) on the falling edge of the signal.

Constraints

Default constraints for the Overshoot - Falling Edge rule
Default constraints for the Overshoot - Falling Edge rule

Maximum (Volts) - the value for the maximum permissible overshoot on the falling edge of the signal.

Rule Application

Batch DRC and during Signal Integrity analysis.


Overshoot - Rising Edge

Default Rule: not required

This rule specifies the maximum allowable overshoot (ringing above the top value) on the rising edge of the signal.

Constraints

Default constraints for the Overshoot - Rising Edge rule
Default constraints for the Overshoot - Rising Edge rule

Maximum (Volts) - the value for the maximum permissible overshoot on the rising edge of the signal.

Rule Application

Batch DRC and during Signal Integrity analysis.


Undershoot - Falling Edge

Default Rule: not required

This rule specifies the maximum allowable undershoot (ringing above the base value) on the falling edge of the signal.

Constraints

Default constraints for the Undershoot - Falling Edge rule
Default constraints for the Undershoot - Falling Edge rule

Maximum (Volts) - the value for the maximum permissible undershoot on the falling edge of the signal.

Rule Application

Batch DRC and during Signal Integrity analysis.


Undershoot - Rising Edge

Default Rule: not required

This rule specifies the maximum allowable undershoot (ringing below the top value) on the rising edge of the signal.

Constraints

Default constraints for the Undershoot - Rising Edge rule
Default constraints for the Undershoot - Rising Edge rule

 

Maximum (Volts) - the value for the maximum permissible undershoot on the rising edge of the signal.

Rule Application

Batch DRC and during Signal Integrity analysis.


Impedance

Default Rule: not required

This rule specifies the minimum and maximum net impedance allowed. Net impedance is a function of the conductor geometry and conductivity, the surrounding dielectric material (the board base material, multi-layer insulation, solder mask, etc) and the physical geometry of the board (distance to other conductors in the z-plane).

Constraints

Default constraints for the Impedance rule
Default constraints for the Impedance rule

  • Minimum (Ohms) - the value for the minimum permissible net impedance.
  • Maximum (Ohms) - the value for the maximum permissible net impedance.
Rule Application

Batch DRC and during Signal Integrity analysis.


Signal Top Value

Default Rule: not required

This rule specifies the minimum voltage level that a signal can settle to in the high state (the top value).

Constraints

Default constraints for the Signal Top Value rule
Default constraints for the Signal Top Value rule

Minimum (Volts) - the value for the minimum permissible top value voltage.

Rule Application

Batch DRC and during Signal Integrity analysis.


Signal Base Value

Default Rule: not required

This rule specifies the maximum voltage level that a signal can settle to in the low state (the base value).

Constraints

Default constraints for the Signal Base Value rule
Default constraints for the Signal Base Value rule

Maximum (Volts) - the value for the maximum permissible base value voltage.

Rule Application

Batch DRC and during Signal Integrity analysis.


Flight Time - Rising Edge

Default Rule: not required

This rule specifies the maximum allowable flight time on signal rising edge. Flight time is the signal delay time introduced by the interconnect structure. It is calculated as the time it takes to drive the signal on the net to the threshold voltage (marking the transition from signal LOW to signal HIGH), less the time it would take to drive a reference load (connected directly to the output) to the threshold voltage.

Constraints

Default constraints for the Flight Time - Rising Edge rule
Default constraints for the Flight Time - Rising Edge rule

Maximum (seconds) - the value for the maximum permissible flight time on the rising edge of the signal.

Rule Application

Batch DRC and during Signal Integrity analysis.


Flight Time - Falling Edge

Default Rule: not required

This rule specifies the maximum allowable flight time on signal falling edge. Flight time is the signal delay time introduced by the interconnect structure. It is calculated as the time it takes for the signal on the net to fall to the threshold voltage (marking the transition from signal HIGH to signal LOW), less the time it would take for a reference load (connected directly to the output) to fall to the threshold voltage.

Constraints

Default constraints for the Flight Time - Falling Edge rule
Default constraints for the Flight Time - Falling Edge rule

Maximum (seconds) - the value for the maximum permissible flight time on the falling edge of the signal.

Rule Application

Batch DRC and during Signal Integrity analysis.


Slope - Rising Edge

Default Rule: not required

This rule specifies the maximum allowable slope time on the rising edge of the signal. Rising edge slope is the time it takes for a signal to rise from the threshold voltage (VT), to a valid high (VIH).

Constraints

Default constraints for the Slope - Rising Edge rule
Default constraints for the Slope - Rising Edge rule

Maximum (seconds) - the value for the maximum permissible rising edge slope time.

Rule Application

Batch DRC and during Signal Integrity analysis.


Slope - Falling Edge

Default Rule: not required

This rule specifies the maximum allowable slope time on the falling edge of the signal. Falling edge slope is the time it takes for a signal to fall from the threshold voltage (VT), to a valid low (VIL). Constraints.

Constraints

Default constraints for the Slope - Falling Edge rule
Default constraints for the Slope - Falling Edge rule

Maximum (seconds) - the value for the maximum permissible falling edge slope time.

Rule Application

Batch DRC and during Signal Integrity analysis.


Supply Nets

Default Rule: not required

This rule identifies a supply net and specifies its voltage (or set of nets using the net class scope).

Constraints

Default constraints for the Supply Nets rule
Default constraints for the Supply Nets rule

Voltage - the voltage value for the net(s) falling under the scope (full query) of the rule.

Rule Application

Batch DRC and during Signal Integrity analysis.

 
 
 
 
 
Note

The supply net(s) can be specified by choosing the Net or Net Class from the drop-down field in the Where The Object Matches region of the PCB Rules and Constraints Editor dialog, and then choosing the required net or net class from the corresponding secondary drop-down list. The corresponding Full Query for the rules' scope will be as follows: InNet('NetName') - for a single net; InNetClass('NetClassName') - for a net class.

Примечание

Доступные функциональные возможности зависят от вашего уровня Подписки на ПО Altium Designer.

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